Parallel processing for decoding and cyclic redundancy checking for the reception of mobile radio signals
View Patent ↗Depending on the sequence of the decoded payload signal bits (a m1 , . . . , a mA ) and redundancy checking bits (p m1 , . . . , p mL ) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device ( 1 ) from the front into a linear feedback shift register ( 10 ), or some of these bits are inserted by means of the distribution device ( 1 ) from the rear into a linear feedback shift register ( 10 ), or all of them are inserted into a linear feedback shift register ( 20 ) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register ( 10; 20 ) without temporary storage of the bits produced by the decoding process.
1. An apparatus for cyclic redundancy checking comprising:
a Viterbi decoder configured to decode a data block comprising payload signal bits and redundancy checking bits from a received signal and to reverse a sequence of the payload signal bits;
a distribution device comprising an input and first and second outputs;
a shift register with linear feedback having first and second inputs, wherein the linear feedback is provided with the first input, wherein the first input is connected to the first output of the distribution device and the second input is connected to the second output of the distribution device; and
wherein the distribution device receives the data block and directs the payload signal bits to the first input of the shift register and directs the redundancy checking bits to the second input of the shift register.
2. The apparatus of claim 1 , further comprising a first contact switch between the first output of the distribution device and the first input of the shift register and a second contact switch between the second output of the distribution device, the second input of the shift register, and a feedback path of the shift register.
3. The apparatus of claim 2 , wherein the second contact switch comprises a first switch position and a second switch position;
in the first switch position, the second contact switch connects the second output of the distribution device with the second input of the shift register; and
in the second switch position, the second contact switch connects the second input of the shift register with an XOR component arranged between the first output of the distribution device and the first contact switch.
4. The apparatus of claim 1 , wherein the shift register comprises a plurality of memory cells connected in series and an OR gate connected to the plurality of memory cells that identifies errors.