Self-addressed subarray precharge
View Patent ↗Power consumption in an integrated circuit memory is reduced by lowering the power supply demand from an on-chip pumped VCCP power source. Only the row decoders for subarrays in a memory bank that were previously activated are precharged in response to a bank precharge command. Additional circuitry is provided to the precharge clock generator circuit. The additional circuitry includes a latch that is set when an array select signal is asserted, and reset when a precharge operation for that bank occurs.
1. A memory comprising:
at least one memory bank including a plurality of subarrays;
a plurality of row decoder circuits associated with the subarrays in the at least one memory bank; and
means for precharging only the row decoder circuits in a subarray that have been previously activated comprising a latch that is set when an array select signal received by the at least one memory bank is asserted, and reset when a precharge operation for the at least one memory bank occurs.
2. The memory of claim 1 wherein the array select signal is unique to each subarray.
3. The memory of claim 1 wherein the precharge operation is unique to the at least one memory bank.
4. A memory comprising:
at least one memory bank including a plurality of subarrays;
a plurality of row decoder circuits associated with the subarrays in the at least one memory bank; and
a precharge clock generator circuit for precharging only the row decoder circuits in a subarray that have been previously activated,
wherein the precharge clock generator further comprises inputs for receiving a precharge signal, an array select signal, and a clock signal, and an output for providing a precharge clock signal.
5. The memory of claim 4 wherein the precharge clock generator circuit comprises a power node for receiving a pumped high voltage.
6. A memory comprising:
at least one memory bank including a plurality of subarrays;
a plurality of row decoder circuits associated with the subarrays in the at least one memory bank; and
means for precharging only the row decoder circuits in a subarray that have been previously activated comprising:
a logic gate for receiving a precharge command;
a transmission gate circuit coupled to the logic gate, having an input for receiving a clock signal;
a latch circuit coupled to the logic gate, having an input for receiving an array select signal; and
a level shifting circuit coupled to the transmission gate circuit and the latch circuit for providing a precharge clock signal.
7. The memory of claim 6 wherein the logic gate comprises a three-input NAND gate.
8. The memory of claim 6 wherein the transmission gate circuit comprises:
a transmission gate having an input for receiving the clock signal, an output coupled to the level shifting circuit, a non-inverting switching input, and an inverting switching input;
an inverter coupled between the non-inverting and inverting switching inputs; and
an N-channel transistor having a gate coupled to the inverting switching input, a source coupled to ground, and a drain coupled to the output of the transmission gate.
9. The memory of claim 8 wherein the transmission gate comprises parallel-coupled N-channel and P-channel transistors.
10. The memory of claim 6 wherein the latch circuit comprises:
an N-channel transistor having a gate for receiving the array select signal, a source coupled to ground, and a drain; and
a latch coupled to the drain of the N-channel transistor.
11. The memory of claim 10 wherein the latch comprises two cross-coupled inverters.
12. The memory of claim 6 wherein the level shifting circuit comprises:
an N-channel transistor having a gate, a source coupled to ground, and a drain coupled to the latch circuit; and
an inverter having an input coupled to the gate of the N-channel transistor, a power node for receiving a pumped high voltage, and an output for providing the precharge clock signal.
13. The memory of claim 6 further comprising a delay circuit interposed between the logic gate and the latch circuit.
14. The memory of claim 13 wherein the delay circuit comprises three serially-coupled inverters.
15. The memory of claim 6 further comprising a delay circuit interposed between the logic gate and the transmission gate circuit.
16. The memory of claim 15 wherein the delay circuit comprises three serially-coupled inverters.
17. A memory comprising:
at least one memory bank including a plurality of subarrays;
a plurality of row decoder circuits associated with the subarrays in the at least one memory bank; and
a precharge clock generator circuit for precharging only the row decoder circuits in a subarray that have been previously activated,
wherein the precharge clock generator circuit comprises a latch that is set when an array select signal received by the at least one memory bank is asserted, and reset when a precharge operation for the at least one memory bank occurs.
18. The memory of claim 17 wherein the precharge clock generator circuit comprises a power node for receiving a pumped high voltage.