IP Library Granted Patent US 7,259,035
Granted Patent B2
US 7,259,035 · App. 11/064,919 · Granted Aug 21, 2007

Methods of forming thin-film transistor display devices

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Quick Facts
Patent No.
US 7,259,035
App. No.
11/064,919
Granted
Aug 21, 2007
Kind
B2
Abstract

Methods of forming thin-film transistor display devices including forming a gate line and a gate electrode on a face of a substrate and forming a semiconductor layer that is insulated from the gate line. A data line and a source/drain electrode are formed on the semiconductor layer. The data line and the source/drain electrode are formed as composites of at least two different metal conductive layers. A transparent pixel electrode is formed that is electrically coupled to the drain electrode.

Claims (36)

1. A method of forming thin-film transistor display device, comprising the steps of:

forming a gate line and a gate electrode on a substrate;

forming a gate insulating layer on the gate line and the gate electrode;

forming a semiconductor layer on the gate insulating layer;

forming a data line including a source electrode and a drain electrode on the semiconductor layer, the data line including the source electrode and the drain electrode comprising a composite of a lower layer of a first metal and an upper layer of a second metal different from the first metal;

forming a pixel electrode electrically coupled to the drain electrode;

forming a gate pad electrically connected to an end portion of the gate line; and

forming a data pad that is electrically connected to an end portion of the data line and contacts an upper surface of the lower layer.

2. The method of claim 1 , wherein the pixel electrode, the gate pad and the data pad are made of the same material.

3. The method of claim 1 , wherein the gate electrode comprises at least two layers including two metals of a different element therein.

4. The method of claim 3 , wherein the gate electrode has a lower layer containing a refractory metal selected from the group comprising chromium, molybdenum, titanium and tantalum and an upper layer containing aluminum on the lower layer of the gate electrode.

5. The method of claim 3 , further comprising:

etching the upper layer to expose the lower layer.

6. The method of claim 1 , wherein the lower layer contains a refractory metal selected from the group comprising chromium, molybdenum, titanium and tantalum and the upper layer contains aluminum.

7. The method of claim 6 , further comprising:

etching the upper layer to expose the lower layer.

8. The method of claim 7 , wherein the pixel electrode contacts the lower layer.

9. The method of claim 1 , wherein the gate pad contacts a side surface of the gate line.

10. The method of claim 1 , wherein the data pad contacts a side surface of the data line.

11. The method of claim 1 , wherein forming the pixel electrode is preceded by:

forming a passivation layer on the data line; and

forming a first contact hole and a second contact hole in the passivation layer;

wherein the first contact hole exposes a lower layer of the drain electrode and the second contact hole exposes a lower layer of the end portion of the data line;

wherein the pixel electrode is formed on the passivation layer and contacts the exposed lower layer of the drain electrode; and

wherein the data pad is formed on the passivation layer and contacts the exposed lower layer of the end portion of the data line.

12. The method of claim 11 , wherein each of the gate electrode and the gate line comprises a lower electrode containing a refractory metal and an upper electrode containing aluminum.

13. The method of claim 12 , further comprising forming a third contact hole in the passivation layer, wherein the third contact hole exposes the lower electrode of an end portion of the gate line.

14. The method of claim 13 , wherein the gate pad is formed on the passivation layer and contacts the exposed lower electrode of the end portion of the gate line.

15. A method of forming thin-film transistor display device, comprising the steps of:

forming a gate electrode on the substrate;

forming a gate insulating layer on the gate electrode;

forming a semiconductor layer on the gate insulating layer;

forming a data line comprising a lower layer of a first metal and an upper layer of a second metal different from the first metal concurrently with forming a source electrode comprising a lower layer of a first metal and an upper layer of the second metal on a first portion of the semiconductor layer;

forming a drain electrode comprising a lower layer of the first metal and an upper layer of the second metal, on a second portion of the semiconductor layer;

forming a pixel electrode that is electrically coupled to the drain electrode and contacts an upper surface of the lower layer of the drain electrode; and

forming a data pad that is electrically connected to an end portion of the data line and contacts an upper surface of the lower layer of the data line.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2014
From: KIM, DONG-GYU
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 031903/0207 →
CHANGE OF NAME Recorded Jan 7, 2014
From: SAMSUNG DISPLAY CO., LTD.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 031927/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029019/0139 →