Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories
View Patent ↗A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.
1. A silicon-oxide-nitride-oxide-silicon (SONOS) memory transistor comprising:
a semiconductor region having a first conductivity type;
a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor region;
a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is entirely covered by one of the word lines;
a first dielectric layer located over the plurality of word lines and the semiconductor region; and
light-absorbing sidewall spacers located over the first dielectric layer, and adjacent to sidewalls of the word lines.
2. The SONOS memory transistor of claim 1 , wherein the light-absorbing sidewall spacers comprise polycrystalline silicon.
3. The SONOS memory transistor of claim 1 , wherein the word lines comprise polycrystalline silicon.
4. The SONOS memory transistor of claim 1 , wherein the first dielectric layer comprises tetra-ethoxy-silane (TEOS).
5. A method of fabricating a fieldless array, the method comprising:
forming an oxide-nitride-oxide (ONO) layer over a surface of a semiconductor region;
patterning the ONO layer to create a first set of ONO structures that define locations for a plurality of diffusion bit lines of the fieldless array;
forming a plurality of word lines over the first set of ONO structures; and
patterning the first set of ONO structures, thereby creating a second set of ONO structures, wherein the second set of ONO structures are located entirely under the plurality of word lines,
forming a first dielectric layer over the word lines and the semiconductor region; and
forming light-absorbing sidewall spacers over the first dielectric layer and adjacent to sidewalls of the word lines.
6. The method of claim 5 , wherein the light-absorbing sidewall spacers comprise polycrystalline silicon.
7. The method of claim 5 , wherein the word lines comprise polycrystalline silicon.
8. The method of claim 5 , wherein the first dielectric layer comprises tetra-ethoxy-silane (TEOS).