Method of changing an electrically programmable resistance cross point memory bit
View Patent ↗Resistive cross point memory devices are provided, along with methods of manufacture and use, including a method of changing an electrically programmable resistance cross point memory bit. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
1. A method of changing resistivity of a bit within a memory array comprising the steps of:
providing the bit formed at the cross point of a word line and a bit line with a perovskite active layer interposed between the word line and the bit line; wherein the bit line is connected through a bit pass transistor having a bit pass gate, to a load transistor, having a load gate, connected to ground;
applying a programming voltage to the word line;
applying a first on voltage to the bit pass gate, whereby current is allowed to flow through the bit pass transistor; and
applying a second on voltage to the load gate, whereby current is allowed to flow through the load transistor, such that current flows through the active layer to change the resistivity of the bit.
2. The method of claim 1 , wherein the programming voltage comprises a plurality of voltage pulses, whereby the resistivity of the bit is changed without damaging the bit.
3. The method of claim 2 , wherein the bit pass transistor is an n-channel transistor and the first on voltage is zero, the load transistor is an n-channel transistor and the second on voltage is zero, and the programming voltage is negative, such that the bit is changed to a first resistivity level.
4. The method of claim 3 , wherein the first resistivity level is a high resistance state.
5. The method of claim 3 , wherein the first resistivity level is a low resistance state.
6. The method of claim 2 , wherein the bit pass transistor is an n-channel transistor and the first on voltage is at a bit pass transistor threshold voltage, the load transistor is an n-channel transistor and the second on voltage is at a load transistor threshold voltage, and the programming voltage is positive, whereby the bit is changed to a second resistivity level.
7. The method of claim 6 , wherein the second resistivity level is a high resistance state.
8. The method of claim 6 , wherein the second resistivity level is a low resistance state.
9. A method of reading a bit having multiple resistivity states within a memory array comprising the steps of:
providing the bit formed at the cross point of a word line and a bit line with a perovskite active layer interposed between the word line and the bit line, wherein the bit line is connected through a bit pass transistor, having a bit pass gate, to an inverter, with a load transistor, having a load gate, connected between the inverter and ground;
applying a readout voltage to the word line;
applying an on voltage to the bit pass gate, whereby current is allowed to flow through the bit pass transistor;
applying a load voltage to the load gate, whereby current above a saturation current of the load transistor is allowed to flow through the load transistor, and current below the saturation current will not flow through the load transistor; and
reading an output voltage from the inverter.
10. The method of claim 9 , wherein the bit is in a low resistance state, whereby a current, which is higher than the saturation current of the load transistor, flows through the bit, and the bit pass transistor, and the load transistor to ground, such that the output voltage of the inverter is approximately zero volts.
11. The method of claim 9 , wherein the bit is in a high resistance state, whereby a current, which is lower than the saturation current of the load transistor, flows through the bit, and the bit pass transistor, but does not flows through the load transistor, such that the output voltage of the inverter is approximately the readout voltage.