Electrically programmable resistance cross point memory circuit
Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
1 - 19 . (canceled)
20 . A memory circuit for a resistive memory bit comprising:
a) a bit line connected to the resistive memory bit;
b) a bit pass transistor, having a gate, a first source/drain and a second source/drain, wherein the first source/drain is connected to the bit line;
c) an inverter, having an input connected to the second source/drain; and
d) a load transistor connected between the inverter and ground, wherein the load transistor has a load gate.
21 . The memory read out circuit of claim Error! Reference source not found., wherein the load gate is biased with a voltage to set a threshold that allows current over a predetermined value to flow through the load transistor.
22 - 44 . (canceled)