Diffusion bias control for improving sensitivity of CMOS active pixel sensors
View Patent ↗In CMOS active pixels there are reverse biased non-photo-detector N type diffusions that attract carriers. These carriers, if not collected by the photo-detector, are effectively lost, and thus the overall sensitivity of the pixel is reduced. This invention provides a method to minimize the bias on non-photo-detector diffusions to minimize the number of wasted carriers and thus improve sensitivity.
1. A method for a CMOS active pixel comprising the steps of;
providing for a photodiode comprising;
a cathode; and,
an anode;
providing for a RESET transistor comprising;
a source;
a drain; and
a gate;
providing for an source follower transistor comprising;
a source;
a drain; and
a gate;
providing for a V dd −rst signal to the source or drain of said reset transistor; and,
providing for a SF bias signal to the source or drain of the said source follower transistor;
holding said V dd −rst signal at a high state at all times; and,
controlling said SF bias signal during integration.
2. The method of claim 1 wherein the controlling step of said SF bias signal during integration comprises holding said SF bias signal at a low state.
3. The method of 2 further comprising the step of providing for one or more additional transistors.
4. The method of claim 1 wherein the controlling step of said SF bias signal during integration comprises pulsing said SF bias signal between a low and high state.
5. The method of 4 further comprising the step of providing for one or more additional transistors.
6. The method of claim 4 wherein the controlling step of said V dd −rst and SF bias signals during integration comprises holding said V dd −rst and SF bias signals at a low state.
7. The method of claim 5 further comprising the step of providing for one or more additional transistors.
8. The method of claim 4 wherein the controlling step of said V dd −rst and SF bias signals during integration comprises pulsing said V dd −rst and SF bias signals between a low and high state.
9. The method of claim 6 further comprising the step of providing for one or more additional transistors.