Granted Patent B2

US 7,634,696 · App. 11/070,970 · Granted Dec 15, 2009

Abstract

Claims (47)

1. A method comprising:

performing a first initializing operation on a memory comprising a plurality of bits to initialize each bit of the plurality of bits to zero;

initializing a first register to all zeros;

retrieving a value, for each of the plurality of bits from the memory after performing the first initializing operation;

applying a logical OR operation to each of the retrieved values with the retrieved value as a first operand and a corresponding value of the first register as a second operand to produce a result value for each application of the logical OR operation;

performing a second initializing operation on the memory to initialize each bit of the plurality of bits to one;

initializing a second register to all ones;

retrieving a value for each of the plurality of bits from the memory after performing the second initializing operation; and

applying a logical AND operation to each of the retrieved values with the retrieved value as a first operand and a corresponding value of the second register as a second operand to produce a result value for each application of the logical AND operation.

2. The method of claim 1 , further comprising:

determining whether a result value of applying the logical OR operation is equal to one or whether a result value of applying the logical AND operation is equal to zero.

3. The method of claim 1 , wherein the method is performed during a boot sequence of a device in which the memory is installed.

4. The method of claim 1 , wherein the method is performed in a portable electronic device in which the memory is installed.

5. The method of claim 4 , wherein the portable electronic device comprises a device for playing media stored using a moving picture experts group audio layer 3 (“MP3”) format.

6. The method of claim 1 , further comprising:

storing result values of applying the logical OR operation in the first register; and

storing result values of applying the logical AND operation in the second register.

7. The method of claim 6 , further comprising

creating a repair control register from the first register and the second register.

8. The method of claim 7 , wherein the repair control register is a binary register having switch values for multiplexers for reading the memory and having switch values for multiplexers for writing to the memory.

9. The method of claim 7 , further comprising using the repair control register to bypass a failed bit during operation of a device in which the memory is installed.

10. A system comprising:

a memory device comprising a plurality of bits;

a processor coupled to the memory system, the processor having access to a test routine executable by the processor, the test routine including instructions to:

perform a first initializing operation on the memory device to initialize each bit of the plurality of bits to zero;

initialize a first register to all zeros;

retrieve a value for each of the plurality of bits from the memory device after performing the first initializing operation;

apply a logical OR operation to each of the retrieved values with the retrieved value as a first operand and a corresponding value of the first register as a second operand to produce a result value for each application of the logical OR operation;

perform a second initializing operation on the memory device to initialize each bit of the plurality of bits to one;

initialize a second register to all ones;

retrieve a value for each of the plurality of bits from the memory device after performing the second initializing operation; and

apply a logical AND operation to each of the retrieved values with the retrieved value as a first operand and a corresponding value of the second register as a second operand to produce a result value for each application of the logical AND operation.

11. The system of claim 10 , wherein the memory device comprises a plurality of multiplexers for reading the plurality of bits and for writing to the plurality of bits.

12. The system of claim 10 , further comprising:

a plurality of multiplexers for reading the plurality of bits and for writing to the plurality of bits; and

a repair control register having switch values for the plurality of multiplexers, wherein the repair control register can switch the multiplexers to ensure that a failed bit does not get written to or read from during operation of the system.

13. The system of claim 10 , further comprising:

a plurality of multiplexers for reading the plurality of bits and for writing to the plurality of bits; wherein the test routine includes instructions to:

store result values of applying the logical OR operation in the first register;

store result values of applying the logical AND operation in the second register;

combine the first register and the second register to yield a repair control register; and

apply the repair control register to the plurality of multiplexers.

14. The system of claim 10 , wherein the test routine includes instructions to:

store result values of applying the logical OR operation in the first register;

store result values of applying the logical AND operation in the second register;

toggle each bit of the second register; and

apply a logical OR operation with the first register as the first operand and the second register as the second operand.

Assignments (20)