2-bit binary comparator and binary comparing device using the same
View Patent ↗A 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary comparator according to an enable signal.
1. A binary comparing device, comprising:
a first 2-bit binary comparator for logically combining a first and a second input signals by using a power voltage as an enable signal; and
a second 2-bit binary comparator for logically combining a third and a fourth input signals by using the output of the first 2-bit binary comparator as an enable signal.
2. The binary comparing device as recited in claim 1 , wherein each 2-bit binary comparator includes:
a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and
an enable unit for outputting a comparison result of the comparison unit as an output of each 2-bit binary comparator according to each enable signal.
3. The binary comparing device as recited in claim 2 , wherein the comparison unit includes:
a first and a second input ports for receiving the first bit and the second bit;
a first and a second PMOS transistors, the first PMOS transistor having a source coupled to the first input port, a gate coupled to a source of the second PMOS transistor and a drain coupled to a first node, the second PMOS transistor having a source coupled to the second input port, a gate coupled to the source of the first PMOS transistor and a drain coupled to the first node; and
a first and a second NMOS transistors, the first NMOS transistor controlled with the first input port and having a first terminal coupled to the first node and a second terminal coupled to a first terminal of the second NMOS transistor, the second NMOS transistor controlled with the second input port and having a second terminal coupled to a ground voltage.
4. The binary comparing device as recited in claim 3 , wherein the enable unit includes:
an enable signal input port for receiving the enable signal;
a third NMOS transistor controlled with the enable signal and having a source coupled to the first node and a drain coupled to a second node; and
a third PMOS transistor controlled with the enable signal and having a source coupled to a power voltage and a drain coupled to the second node.
5. The binary comparing device as recited in claim 4 , further comprising an inverter for inverting the logic value of the second node.