IP Library Granted Patent US 7,570,245
Granted Patent B2
US 7,570,245 · App. 11/071,537 · Granted Aug 4, 2009

Control unit and method for reducing interference patterns in the display of an image on a screen

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Quick Facts
Patent No.
US 7,570,245
App. No.
11/071,537
Granted
Aug 4, 2009
Kind
B2
Abstract

A control unit and a method are provided to reduce an interference pattern in the display of an image on a screen with a pixel frequency. The image is described by pixel data and provided to the screen by a control unit. During the generation of pixel data, the clock signals used in the generation of the pixel data are varied or the pixel frequency is changed.

Claims (19)

1. A method for reducing interference patterns in the display of an image on a screen with a pixel frequency, wherein the image can be described by pixel data, which are provided to the screen by a control unit based on received image data, wherein the control unit has an input for receiving the image data and a plurality of clock signals, wherein one or more of the clock signals couples into the control unit via the input and overlays the image data, the method comprising:

during the generation of pixel data, varying one or several of the clock signals used in generating the pixel data by time-dependent frequency modulation,

wherein the time-dependent frequency modulation is time-discrete over a row or a frame of the pixel data, and the frequency is changed in a change of rows or a change of frames.

2. The method according to claim 1 , wherein during the generation of the pixel data the pixel frequency is changed.

3. The method according to claim 1 , wherein the control unit comprises a pixel frequency generator, which generates the pixel frequency depending on an applied input frequency, wherein the step of changing the pixel frequency comprises changing the input frequency.

4. The method according to claim 3 , wherein the input frequency is provided by an external frequency source or by an internal frequency source of the control unit.

5. The method according to claim 3 , wherein the control unit comprises a memory interface, which is driven by a driving signal with a memory frequency, and a memory frequency generator, wherein the input frequency of the pixel frequency generator is further applied to the memory frequency generator.

6. The method according to claim 3 , wherein the pixel frequency generator comprises a spread spectrum phase locked loop.

7. A control unit for controlling a screen, which operates at a pixel frequency, for the display of an image on the screen with reduced interference pattern, wherein the control unit comprises a plurality of clock signals, comprising

an input for receiving image data, wherein one or more of the clock signals couples into the control unit via the input and is overlaid with the image data;

a processor, which processes the received image data for generating the pixel data, wherein the processor varies one or several of the clock signals used in generating the pixel data during the generation of the pixel data by time-dependent frequency modulation; and

an output for providing the pixel data for the display,

wherein the time-dependent frequency modulation is time-discrete over a row or a frame of the pixel data, and

wherein the processor causes a change of the frequency in a change of rows or a change of frames.

8. The control unit according to claim 7 , wherein the processor changes the pixel frequency during the generation of the pixel data.

9. the control unit according to claim 7 , wherein the processor comprises a pixel frequency generator, which generates the pixel frequency depending on a changing input frequency signal.

10. The control unit according to claim 9 , wherein the variable input frequency signal is provided by an external signal source or by an internal frequency control based on an external constant frequency signal.

11. The control unit according to claim 9 , wherein the processing unit comprises a memory frequency generator, which generates a memory frequency for a driving signal for a memory interface, based on the input frequency signal.

12. The control unit according to claim 9 , wherein the pixel frequency generator comprises a spread spectrum phase locked loop.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2021
From: MUFG UNION BANK, N.A.
To: MAXLINEAR, INC.; EXAR CORPORATION; MAXLINEAR COMMUNICATIONS LLC
Reel/Frame 056656/0204 →
SUCCESSION OF AGENCY (REEL 042453 / FRAME 0001) Recorded Jul 1, 2020
From: JPMORGAN CHASE BANK, N.A.
To: MUFG UNION BANK, N.A.
Reel/Frame 053115/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2018
From: MAXLINEAR INC; ENTROPIC COMMUNICATIONS LLC
To: DYNAMIC DATA TECHNOLOGIES LLC
Reel/Frame 047128/0295 →
SECURITY AGREEMENT Recorded May 12, 2017
From: MAXLINEAR, INC.; ENTROPIC COMMUNICATIONS, LLC (F/K/A ENTROPIC COMMUNICATIONS, INC.); EXAR CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042453/0001 →
MERGER AND CHANGE OF NAME Recorded May 19, 2015
From: ENTROPIC COMMUNICATIONS, INC.; EXCALIBUR SUBSIDIARY, LLC; ENTROPIC COMMUNICATIONS, LLC
To: ENTROPIC COMMUNICATIONS, LLC
Reel/Frame 035717/0628 →
MERGER AND CHANGE OF NAME Recorded May 18, 2015
From: EXCALIBUR ACQUISITION CORPORATION; ENTROPIC COMMUNICATIONS, INC.; ENTROPIC COMMUNICATIONS, INC.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 035706/0267 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: TRIDENT MICROSYSTEMS, INC.; TRIDENT MICROSYSTEMS (FAR EAST) LTD.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 028153/0440 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: NXP
To: NXP HOLDING 1 B.V.
Reel/Frame 023928/0489 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: TRIDENT MICROSYSTEMS (EUROPE) B.V.; NXP HOLDING 1 B.V.
To: TRIDENT MICROSYSTEMS (FAR EAST) LTD.
Reel/Frame 023928/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2008
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 021085/0959 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2005
From: ENGELHARDT, OLIVER; ECKHARDT, ANDREAS
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 016339/0001 →