Display driver circuit and drive method thereof
View Patent ↗There is provided a technology that can reduce the number of signal lines by encoding a PWM signal used in a display driver IC. The display driver circuit for displaying a gradation on a display screen based on a PWM signal includes a PWM signal generator for generating a PWM signal, a PWM encoder for encoding the PWM signal generated from the PWM signal generator, a PWM decoder for decoding the encoded PWM signal into the PWM signal, a switching unit for selectively outputting the PWM signal generated from the PWM decoder, a data storage unit for storing a display data used to switch the switching unit, and an SRAM decoder for outputting an on/off signal to the switching unit according to the display data outputted from the data storage unit.
1. A display driving method for displaying a gradation on a display screen based on 2 n PWM signals, the display driving method comprising:
encoding the 2 n PWM signals to generate n encoded PWM signals;
transferring (n+1) signals including the n encoded PWM signals and one PWM signal having a longest pulse width through (n+1) signal lines;
receiving the (n+1) signals and decoding the n encoded PWM signals based on one PWM signal having a longest pulse width to generate decoded 2 n PWM signals; and
displaying the gradation on the display screen based on the decoded 2 n PWM signals, wherein n is an integer greater than or equal to 2.
2. The display driving method as recited in claim 1 , wherein in the case of a 256-color display, the encoding of the 2 n PWM signals generates 3 signals, based on 8 PWM signals (PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6 and PW 7 , whose pulse widths become longer from PW 0 to PW 7 in this order), the 3 signals being given by a Boolean algebra expression below
E 0= PW 0 · PW 1+ PW 2 · PW 3+ PW 4 · PW 5+ PW 6 · PW 7
E 1= PW 1 · PW 3+ PW 5 · PW 7
E 2= PW 3 · PW 7.
3. The display driving method as recited in claim 2 , wherein the decoding of the n encoded PWM signals based on one PWM signal having a longest pulse width includes:
generating an intermediate signal by using a Boolean algebra expression below; and
D 0= PW 7· E 2 · E 1 · E 0
D 1= PW 7· E 2 · E 1 · E 0
D 2= PW 7· E 2 · E 1· E 0
D 3= PW 7· E 2 · E 1· E 0
D 4= PW 7· E 2· E 1 · E 0
D 5= PW 7· E 2· E 1 · E 0
D 6= PW 7· E 2· E 1· E 0
D7=PW7
decoding the intermediate signal into a final PWM signal by using a Boolean algebra expression below
PW0=D0
PW 1= PW 0+ D 1
PW 2= PW 1+ D 2
PW 3= PW 2+ D 3
PW 4= PW 3+ D 4
PW 5= PW 4+ D 5
PW 6= PW 5+ D 6
PW7=D7.
4. The display driving method as recited in claim 1 , wherein the display is a liquid crystal display (LCD).
5. A display driver circuit for displaying a gradation on a display screen based on 2 n PWM signals, the display driver circuit comprising:
a PWM signal generator for generating the 2 n PWM signals;
a PWM encoder for encoding the 2 n PWM signals generated from the PWM signal generator to generate n encoded PWM signals;
(n+1) signal lines for transferring (n+1) signals including the n encoded PWM signals and one PWM signal having a longest pulse width;
a PWM decoder for receiving the (n+1) signals and decoding the n encoded PWM signals based on one PWM signal having a longest pulse width to generate decoded the 2 n PWM signals;
a switching unit for selectively outputting the decoded 2 n PWM signals generated from the PWM decoder;
a data storage unit for storing a display data used to switch the switching unit; and
an SRAM decoder for outputting an on/off signal to the switching unit according to the display data outputted from the data storage unit,
wherein n is an integer greater than or equal to 2.
6. The display driver circuit as recited in claim 5 , wherein in the case of a 256-color display, the PWM encoder generates 3 signals, based on 8 PWM signals (PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6 and PW 7 , whose pulse widths become longer from PW 0 to PW 7 in this order), the 3 signals being given by a Boolean algebra expression below
E 0= PW 0 · PW 1+ PW 2 · PW 3+ PW 4 · PW 5+ PW 6 · PW 7
E 1= PW 1 · PW 3+ PW 5 · PW 7
E 2= PW 3 · PW 7.
7. The display driver circuit as recited in claim 6 , wherein the PWM decoder generates an intermediate signal by using a Boolean algebra expression below
D 0= PW 7· E 2 · E 1 · E 0
D 1= PW 7· E 2 · E 1 · E 0
D 2= PW 7· E 2 · E 1· E 0
D 3= PW 7· E 2 · E 1· E 0
D 4= PW 7 ·E 2· E 1 · E 0
D 5= PW 7· E 2· E 1 · E 0
D 6= PW 7· E 2· E 1· E 0
D7=PW7
and decodes the intermediate signal into a final PWM signal by using a Boolean algebra expression below
PW0=D0
PW 1= PW 0+ D 1
PW 2= PW 1+ D 2
PW 3= PW 2+ D 3
PW 4= PW 3+ D 4
PW 5= PW 4+ D 5
PW 6= PW 5+ D 6
PW7=D7.
8. The display driver circuit as recited in claim 5 , wherein the PWM signal generator and the PWM encoder are integrated into one block.
9. The display driver circuit as recited in claim 8 , wherein the display is a liquid crystal display (LCD).
10. The display driver circuit as recited in claim 5 , wherein the PWM decoder and the SRAM decoder are integrated into one decoder.
11. The display driver circuit as recited in claim 10 , wherein the display is a liquid crystal display (LCD).
12. The display driver circuit as recited in claim 5 , wherein the display is a liquid crystal display (LCD).