IP Library Granted Patent US 8,022,906
Granted Patent B2
US 8,022,906 · App. 11/072,205 · Granted Sep 20, 2011

Driver for use in a flat panel display adapted to drive segment lines using a current

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Quick Facts
Patent No.
US 8,022,906
App. No.
11/072,205
Granted
Sep 20, 2011
Kind
B2
Abstract

A driver for use in a flat panel display, the driver adapted to drive segment lines by using a current, the current being generated by referring to a reference current outputted from a reference current source, the driver includes a driving block selector for selecting a reference current driving block to be activated according to a reference current value with respect to the reference current; and a plurality of reference current driving blocks for transferring the reference current value to a part where the segment lines are driven.

Claims (20)

1. A driver for use in a flat panel display comprising:

a plurality of reference current driving blocks, each of the reference current driving blocks including a first current mirror that comprises a pair of low-voltage NMOS transistors for generating a first mirroring current by mirroring a reference current output from a reference current source;

a plurality of driving block selectors for selecting one pair of the low-voltage NMOS transistors in one of the reference current driving blocks to be activated according to a turn-on signal, and for transferring the reference current to the selected reference current driving block, wherein the turn-on signal is generated by grouping a range of digital pixel data into a predetermined number, and the turn-on signal is transmitted to a designated driving block selector when a digital value of the grouped range is inputted; and

at least one channel, each channel including a second current mirror that comprises high-voltage PMOS transistors,

wherein the first mirroring current flows from a corresponding one of the low-voltage NMOS transistors to a corresponding one of the high-voltage PMOS transistors to generate a second mirroring current, and

at least one channel switch coupled between the first and second current mirrors to select a segment line from among a plurality of segment lines,

wherein the low-voltage NMOS transistors occupy a smaller area than the high-voltage PMOS transistors,

wherein the reference current driving blocks and the driving block selectors are formed on a reference substrate area disposed at a center of a segment line controller, and the channel is formed on a channel substrate area located at both sides of the reference substrate area,

wherein a high-voltage PMOS transistor has a small incremental amount of a current with respect to the voltage, and

wherein a low-voltage NMOS transistor has a large incremental amount of a current with respect to the voltage.

2. The driver as recited in claim 1 , wherein the driving block selector receives a digital value of a pixel data, which is prior to a conversion into the reference current value, and selects one of the reference current driving blocks.

3. The driver as recited in claim 1 , wherein the low-voltage NMOS transistors operate in a range from approximately 2.5 V to approximately 3.0 V.

4. The driver as recited in claim 1 , wherein the high-voltage PMOS transistors operate in a range of approximately 18 V.

5. The driver as recited in claim 1 , wherein the first current minor includes:

a first NMOS transistor having a drain receiving the reference current, a gate connected to the drain, and a source grounded; and

a second NMOS transistor having a gate connected to the gate of the first NMOS transistor, a source grounded, and a drain outputting the first minoring current.

6. The driver as recited in claim 1 , wherein the second current mirror includes:

a first PMOS transistor having a source connected to a high voltage, a drain receiving the first mirroring current, and a gate connected to the drain; and

a second PMOS transistor having a source connected to the high voltage, a gate connected to the gate of the first PMOS transistor, and a drain outputting the second mirroring current.

7. The driver as recited in claim 1 , the channel switch includes a channel switching transistor having a gate receiving an on/off control signal, a drain coupled to the second current mirror, and a source coupled to the first current mirror.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2025
From: MAGNACHIP MIXED-SIGNAL, LTD.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 071813/0800 →
NUNC PRO TUNC ASSIGNMENT Recorded Mar 14, 2024
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: MAGNACHIP MIXED-SIGNAL, LTD.
Reel/Frame 066878/0875 →
RELEASE OF SECURITY INTEREST Recorded Aug 12, 2013
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 030988/0419 →