Semiconductor integrated circuit device
View Patent ↗To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
1. A semiconductor integrated circuit device comprising:
a first nonvolatile memory cell and a second nonvolatile memory cell, each comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type;
a source region and a drain region of the second conductivity type formed on the first semiconductor region; and
a gate electrode formed on the first semiconductor region and the second semiconductor region, a insulating film placed between the gate electrode and the first and second semiconductor regions; and
a control circuit to generate a control signal for writing or reading the first and second nonvolatile memory cells; and
wherein the control circuit is placed near the first nonvolatile memory cell in a first direction;
wherein a signal line for providing the control signal to the first and second nonvolatile memory cells extend in the first direction.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the first nonvolatile memory cell and the second nonvolatile memory cell share a control gate.