Semiconductor device including a high voltage transistor
View Patent ↗A drain diffusion layer 11 b includes a low impurity concentration region 5 a and a high impurity concentration region 5 b , and the low impurity concentration region 5 a is located on the channel region side. An impurity layer 7 having an opposite conductivity type to the drain diffusion layer 11 b is formed in the channel region, at a position away from the low impurity concentration region 5 a by a distance T. Alternatively, the low impurity concentration region 5 a and the impurity layer 7 are located so as to contact each other. Still alternatively, a border impurity layer is provided between the low impurity concentration region 5 a and the impurity layer 7 . Thus, a semiconductor device including a high voltage transistor capable of suppressing the reduction of the electric current driving capability and performing stable driving, and a method for fabricating the same, can be provided.
1. A semiconductor device including a high voltage transistor, the semiconductor device comprising:
a semiconductor substrate having a first conductivity type surface portion;
a second conductivity type source diffusion layer formed in the semiconductor substrate;
a drain diffusion layer including a second conductivity type low impurity concentration region and a second conductivity type high impurity concentration region having a higher impurity concentration than that of the low impurity concentration region, wherein the low impurity concentration region is formed on the side of the source diffusion layer;
a first conductivity type impurity layer provided between the source diffusion layer and the low impurity concentration region in the semiconductor substrate;
a gate insulating film provided on the first conductivity type impurity layer; and
a gate electrode provided on the gate insulating film;
wherein the low impurity concentration region and the impurity layer are positioned so as not to compensate for the impurity of each other.
2. A semiconductor device according to claim 1 , wherein the low impurity concentration region and the impurity layer are discrete from each other.
3. A semiconductor device according to claim 1 , wherein the low impurity concentration region and the impurity layer contact each other.
4. A semiconductor device according to claim 1 , further comprising a second conductivity type border impurity layer between the low impurity concentration region and the impurity layer.
5. A semiconductor device according to claim 1 , further comprising an insulating film for device isolation in the semiconductor substrate, wherein the low impurity concentration region is provided below the insulating film.
6. A semiconductor device according to claim 1 , wherein the low impurity concentration region and the impurity layer do not overlap each other in a vertical direction.