Methods for manufacturing SOI substrate using wafer bonding and complementary high voltage bipolar transistor using the SOI substrate
View Patent ↗A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.
1. A SOI structure made by the method comprising:
providing a first substrate with a first device region containing a first lightly doped impurity region containing a first highly doped impurity region and a second device region containing a second lightly doped impurity region containing a second highly doped impurity region therein;
forming two substantially similar first trenches between the first and second device regions in the first substrate, wherein the depth of the first trenches is deeper than the highly doped impurity regions and shallower than the lightly doped impurity regions;
forming two substantially similar second trenches in the first trenches by forming an insulating layer on the surfaces of the first trenches;
providing a second substrate on the insulating layer;
removing a portion of the first substrate sufficient to expose the first trenches; and
forming a first device in the first device region and forming a second device in the second region, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors.
2. A SOI structure made by the method comprising:
providing a first substrate with a first device region containing a first lightly doped impurity region containing a first highly doped impurity region therein and a second device region containing a second lightly doped impurity region containing a second highly doped impurity region therein;
forming two substantially similar first trenches between the first and second device regions in the first substrate, wherein the depth of the first trenches is deeper than the highly doped impurity regions and shallower than the lightly doped impurity regions;
forming two substantially similar second trenches in the first trenches by forming an insulating layer on the surfaces of the first trenches;
forming a polycrystalline silicon layer to fill the second trenches;
forming a second insulating layer on the polycrystalline silicon layer;
providing a second substrate on the second insulating layer;
removing a portion of the first substrate to expose the first insulating layer; and forming a first device in the first device region and forming a second device in the second region, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors.
3. A semiconductor device made by the method comprising:
providing a first substrate with a first device region containing a first lightly doped impurity region containing a first highly doped impurity region therein and a second device region containing a second lightly doped impurity region containing a second highly doped impurity region therein;
forming two substantially similar first trenches between the first and second device regions in the first substrate, wherein the depth of the first trenches is deeper than the highly doped impurity regions and shallower than the lightly doped impurity regions;
forming two substantially similar second trenches in the first trenches by forming an insulating layer on the surfaces of the first trenches;
providing a second substrate on the insulating layer;
removing a portion of the first substrate sufficient to expose the first trenches; and forming a first device in the first device region and forming a second device in the second region, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors.
4. A semiconductor device made by the method comprising:
providing a first substrate with a first device region containing a first lightly doped impurity region containing a first highly doped impurity region therein and a second device region containing a second lightly doped impurity region containing a second highly doped impurity region therein;
forming two substantially similar first trenches between the first and second device regions in the first substrate, wherein the depth of the first trenches is deeper than the highly doped impurity regions and shallower than the lightly doped impurity regions;
forming two substantially similar second trenches in the first trenches by forming an insulating layer on the surfaces of the first trenches;
forming a polycrystalline silicon layer to fill the second trenches;
forming a second insulating layer on the polycrystalline silicon layer;
providing a second substrate on the second insulating layer;
removing a portion of the first substrate to expose the first insulating layer; and forming a first device in the first device region and forming a second device in the second region, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors.
5. The SOI structure of claim 1 , the method further comprising providing a polysilicon layer in the second trenches.
6. The SOI structure of claim 5 , the method further comprising providing a second insulating layer over the polysilicon layer.
7. The SOI structure of claim 6 , the method further comprising planarizing the second insulating layer.
8. The device of claim 3 , the method further comprising providing a polysilicon layer in the second trenches.
9. The device of claim 8 , the method further comprising providing a second insulating layer over the polysilicon layer.
10. The device of claim 9 , the method further comprising planarizing the second insulating layer.
11. The SOI structure of claim 2 , the method further comprising a process of planarizing the upper surface of the polycrystalline silicon layer.
12. The SOI structure of claim 11 , wherein the process of planarizing is performed by a chemical mechanical polishing.
13. The SOI structure of claim 2 , wherein the removal process comprises removing enough of the first substrate to expose the first and second lightly doped impurity regions and then removing enough of the first substrate to expose the first insulating layer.
14. The SOI structure of claim 2 , wherein the second substrate does not comprise an epitaxial layer.
15. The device of claim 4 , the method further comprising a process of planarizing the upper surface of the polycrystalline silicon layer.
16. The device of claim 15 , wherein the process of planarizing is performed by a chemical mechanical polishing.
17. The device of claim 4 , wherein the removal process comprises removing enough of the first substrate to expose the first and second lightly doped impurity regions and then removing enough of the first substrate to expose the first insulating layer.
18. The device of claim 4 , wherein the second substrate does not comprise an epitaxial layer.
19. An SOI structure comprising:
a substrate not containing an epitaxial layer;
a first device in a first device region with a first dopant region containing an upper region having a low concentration of a first impurity and a lower region having a high concentration of a first impurity, wherein the first dopant region forms part of a PNP transistor;
a second device in a second device region with a second dopant region containing an upper region having a low concentration of a second impurity and a lower region having a high concentration of a second impurity, wherein the second region forms part of a NPN transistor; and
an insulating region isolating the substrate, first device region, and second device region, the insulating region comprising two substantially similar adjacent trenches containing a polysilicon layer;
wherein the first device and the second device are adjacent each other and comprise a complementary bipolar transistor device.
20. A SOI structure, comprising:
a substrate not containing an epitaxial layer;
a first device in a first device region with a first dopant region containing an upper region having a low concentration of a first impurity and a lower region having a high concentration of a first impurity;
a second device in a second device region with a second dopant region containing an upper region having a low concentration of a second impurity and a lower region having a high concentration of a second impurity, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors; and
an insulating region isolating the substrate, first device region, and second device region, the insulating region containing a conductive layer within two substantially similar adjacent trenches.
21. The SOI structure of claim 20 , wherein the conductive layer has a substantially planar surface.
22. The SOI structure of claim 20 , wherein each of the trenches containing the conductive layer are located within another trench containing an insulating layer.
23. The SOI structure of claim 20 , wherein the first and second dopant regions have an upper surface substantially planar with an upper surface of the insulating layer.
24. The SOI structure of claim 20 , wherein the first dopant region forms part of a PNP transistor and the second region forms part of a NPN transistor.
25. The SOI structure of claim 24 , wherein the SOI structure is part of a complementary bipolar transistor device.