Polarity-insensitive signal detect circuit for use with any signal sequence
View Patent ↗A signal detect circuit includes a signal strength measuring differential output linear amplifier. A positive peak detection circuit is coupled to the positive output terminal of the linear amplifier and generates a signal that represents a peak magnitude of a signal received from the positive output terminal. Likewise, a negative peak detection circuit is coupled to the negative output terminal of the linear amplifier and generates a signal that represents a peak magnitude of a signal received from the negative output terminal. Upon power up of the signal detect circuit, a comparison circuit detects when the positive and negative peak signal magnitudes has both exceed respective values at least once. Once this occurs, the comparison circuit compares an interpolation of the positive peak signal and the negative peak signal with the value. If the interpolated signal falls below the value, the comparison circuit generates a signal representing that no signal is being received.
1. An optical transceiver comprising:
an optical receiver;
an optical transmitter; and
a signal detect circuit comprising the following:
a signal strength measuring differential output linear amplifier having a positive and a negative output terminal;
a positive peak detection circuit coupled to the positive output terminal of the linear amplifier, wherein the positive peak detection circuit is configured to generate on its output terminal a positive peak signal that represents a peak magnitude of a peak of a signal received from the positive output terminal of the linear amplifier;
a negative peak detection circuit coupled to the negative output terminal of the linear amplifier, wherein the negative peak detection circuit is configured to generate on its output terminal a negative peak signal that represents a peak magnitude of a peak of a signal received from the negative output terminal of the linear amplifier; and
a comparison circuit configured, upon power up, to detect when the positive peak signal magnitude has exceeded a first value and when the negative peak signal magnitude has exceeded a second value, wherein the comparison circuit is further configured to thereafter compare an interpolation of the positive peak signal and the negative peak signal with a third value, wherein the comparison circuit is configured to generate a signal representing that no signal is being received at the signal strength measuring differential output linear amplifier if the interpolation is below the third value.
2. An optical transceiver in accordance with claim 1 , wherein the first value and the second value are the same.
3. An optical transceiver in accordance with claim 2 , wherein the first value and the third value are the same.
4. An optical transceiver in accordance with claim 1 , wherein the second value and the third value are the same.
5. An optical transceiver in accordance with claim 1 , wherein the linear amplifier has a feedback loop that tends to nullify offset of the linear amplifier.
6. An optical transceiver in accordance with claim 1 , wherein the comparison circuit further comprises a switch that couples the output terminal of the positive peak detection circuit with the output terminal of the negative peak detection circuit, wherein the comparison circuit is configured to have the switch open until both the positive peak signal magnitude is detected to exceed the first value and the negative peak signal magnitude is detected to exceed the second value.
7. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is part of a telecommunications system.
8. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is a 1 G optical transceiver.
9. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is a 2.5 G optical transceiver.
10. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is a 4 G optical transceiver.
11. An optical transceiver in accordance with claim 1 , wherein optical transceiver is a 10 G laser transceiver.
12. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is suitable for fiber channels greater than 10 G.
13. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is part of an XFP laser transceiver.
14. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is part of an SFP laser transceiver
15. An optical transceiver in accordance with claim 1 , wherein the optical transceiver is part of an SFF laser transceiver.
16. An optical transceiver comprising: a signal detect circuit comprising the following: a signal strength measuring linear amplifier having a positive and a negative output terminal, wherein the signal strength measuring amplifier receives an input signal; a positive peak detection circuit coupled to the positive output terminal of the linear amplifier, wherein the positive peak detection circuit is configured to generate on its output terminal a positive peak signal that represents a peak magnitude of a peak of a signal received from the positive output terminal of the linear amplifier; a negative peak detection circuit coupled to the negative output terminal of the linear amplifier, wherein the negative peak detection circuit is configured to generate on its output terminal a negative peak signal that represents a peak magnitude of a peak of a signal received from the negative output terminal of the linear amplifier; and a comparison circuit configured, upon power up, to detect when the positive peak signal magnitude has exceeded a first value and when the negative peak signal magnitude has exceeded a second value, wherein the comparison circuit is further configured to thereafter compare an interpolation of the positive peak signal and the negative peak signal with a third value, wherein the comparison circuit generates a signal representing that the input signal is not being received if the interpolation is below the third value.
17. The optical transceiver of claim 16 , wherein the comparison circuit further comprises;
a switch that couples the output terminal of the positive peak detection circuit with the output terminal of the negative peak detection circuit after the positive peak signal magnitude and the negative peak signal magnitude independently exceed the corresponding first and second values and a comparator that compares the interpolation with the third value.
18. The optical transceiver of claim 16 , further comprising an offset nullification signal to reduce an offset of the signal strength measuring amplifier.
19. An optical transceiver comprising a signal detect circuit comprising: a signal strength measuring differential output linear amplifier having a positive and a negative output terminal;
a positive peak detection circuit coupled to the positive output terminal of the linear amplifier, wherein the positive peak detection circuit is configured to generate on its output terminal a positive peak signal that represents a peak magnitude of a peak of a signal received from the positive output terminal of the linear amplifier;
a negative peak detection circuit coupled to the negative output terminal of the linear amplifier, wherein the negative peak detection circuit is configured to generate on its output terminal a negative peak signal that represents a peak magnitude of a peak of a signal received from the negative output terminal of the linear amplifier; and
a comparison circuit configured to operate in a first operational state to detect when the positive peak signal magnitude has exceeded a first value and when the negative peak signal magnitude has exceeded a second value, the comparison circuit further being configured to operate in a second operational state to determine if a signal is being received at the signal strength measuring differential output linear amplifier by comparing an interpolation of the positive peak signal and the negative peak signal with a third value,
wherein the comparison circuit comprises logic configured to switch the comparison circuit from the first operational state to the second operational state.