IP Library Granted Patent US 7,332,928
Granted Patent B2
US 7,332,928 · App. 11/074,607 · Granted Feb 19, 2008

Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit

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Quick Facts
Patent No.
US 7,332,928
App. No.
11/074,607
Granted
Feb 19, 2008
Kind
B2
Abstract

A circuit module having one of more digital input terminals that are capable of receiving a third input state to initiate non-standard operational modes such as might be desired during programming or testing of the module or its surrounding circuitry. For each of these special digital input terminals, there is a component that recognizes the presence of the third state applied to the corresponding input terminal. In response, the component generates a signal that causes the module to enter the non-standard operational mode. A non-standard operational mode is a mode other than the normal operational mode of the module. As an example, the non-standard operational mode might be a testing or programming mode that is encountered prior to even shipping the module to a consumer.

Claims (26)

1. A circuit module comprising the following:

at least one digital input terminal, the circuit module being configured to be in a standard operational mode when a first or second state is applied to the digital input terminal; and

an alternate special operation detector component configured to receive digital input signals applied to the digital input terminal and cause the circuit module to enter a non-standard operational mode when a third state is applied to the digital input terminal, wherein the non-standard operational mode is a programming mode and wherein the circuit module is configured to abstain from communicating with an external memory during the programming mode.

2. A circuit module in accordance with claim 1 , wherein the circuit module is configured to allow internal memory to be programmed during the programming mode.

3. A circuit module in accordance with claim 1 , wherein the circuit module is incorporated into a telecommunications system.

4. A circuit module in accordance with claim 1 , wherein the circuit module is incorporated into an optical transceiver.

5. A circuit module in accordance with claim 1 , wherein the digital input terminal is a first digital input terminal, and the at least one digital input terminal comprises a second digital input terminal, wherein the second digital input terminal is coupled to a standard function when the circuit module is in the standard operational mode, and is coupled to an alternate function when the circuit module is in the non-standard operational mode.

6. A circuit module in accordance with claim 5 , wherein when the second digital input terminal is coupled to the alternative function, a default value is provided to the standard function.

7. A circuit module comprising the following:

a first digital input terminal, the circuit module being configured to be in a first standard operational mode when a first or second state is applied to the first digital input terminal;

a first non-standard operation initiation component configured to receive digital input signals applied to the first digital input terminal and cause the circuit module to enter a first non-standard operational mode when a third state is applied to the first digital input terminal;

a second digital input terminal, the circuit module being configured to be in a second standard operational mode when a first or second state is applied to the second digital input terminal; and

a second non-standard operation initiation component configured to receive digital input signals applied to the second digital input terminal and cause the circuit module to enter a second non-standard operational mode when a third state is applied to the first digital input terminal.

8. A circuit module in accordance with claim 7 , wherein the first or second non-standard operational mode is a testing mode for testing the circuit module.

9. A circuit module in accordance with claim 8 , wherein the circuit module is configured to operate using a test clock signal during the testing mode.

10. A circuit module in accordance with claim 7 , wherein the first or second non-standard operational mode is a programming mode.

11. A circuit module in accordance with claim 10 , wherein the circuit module is configured to allow internal memory to be programmed during the programming mode.

12. A circuit module in accordance with claim 10 , wherein the circuit module is configured to abstain from communicating with an external memory during the programming mode.

13. A circuit module in accordance with claim 7 , wherein the second digital input terminal is coupled to a standard function when the circuit module is in the standard operational mode, and is coupled to an alternate function when the circuit module is in the non-standard operational mode.

14. A circuit module in accordance with claim 13 , wherein when the second digital input terminal is coupled to the alternative function, a default value is provided to the standard function.

15. A circuit module comprising the following:

first and second digital input terminals, the circuit module being configured to be in a standard operational mode when a first or second state is applied to the first digital input terminal; and

a non-standard operation initiation component configured to receive digital input signals applied to the first digital input terminal and cause the circuit module to enter a non-standard operational mode when a third state is applied to the first digital input terminal, wherein the second digital input terminal is coupled to a standard function when the circuit module is in the standard operational mode, and is coupled to an alternate function when the circuit module is in the non-standard operational mode.

16. A circuit module in accordance with claim 15 , wherein the non-standard operational mode is a testing mode for testing the circuit module.

17. A circuit module in accordance with claim 16 , wherein the circuit module is configured to operate using a test clock signal during the testing mode.

18. A circuit module in accordance with claim 15 , wherein when the second digital input terminal is coupled to the alternative function, a default value is provided to the standard function.

Assignments (4)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →