Semiconductor integrated circuit having test circuitry with reduced power consumption
View Patent ↗The present invention provides a semiconductor integrated circuits that can prevent causes arising a problem of the power consumption during the normal operation thereof. Solution: The present invention relates to a semiconductor integrated circuit having a plurality of memory device of the scan thereof having functions to output the status values during the scan test therein. At least, a part of the memory device of the scan includes a first signal-outputting unit outputting a signal during the normal operation therein and a second signal-outputting unit outputting a signal during the scan test operation therein, respectively. Where, it is preferable that the first signal-outputting unit has a larger driving capacity to signal lines therein than the second signal-outputting unit, and that a second signal-outputting unit fixes the output signal level during the normal operation thereof, and that the second signal-outputting unit outputs a status value delayed a predetermined period of the operation clock therein compared with the first signal-outputting unit during the scan test thereof, and so on.
1. A semiconductor integrated circuit having a test mode and a normal operation mode, comprising:
a plurality of scan memory devices which output status values during a scan test operation in the test mode, each scan memory device including
a first signal-outputting unit, that outputs a signal during the normal operation mode; and
a latch circuit serving as a second signal-outputting unit that outputs a signal on a scan path during the scan test operation.
2. The semiconductor integrated circuit according to claim 1 , wherein said first signal-outputting unit has a larger driving capacity to signal lines than said second signal-outputting unit.
3. The semiconductor integrated circuit according to claim 2 , wherein said second signal-outputting unit outputs said status values delayed by a predetermined period of an operation clock from a timing of outputting said status values by said first signal-outputting unit during said test mode operation.
4. The semiconductor integrated circuit according to claim 1 , wherein said second signal-outputting unit fixes an output signal level during said normal operation mode.
5. The semiconductor integrated circuit according to claim 4 , wherein said second signal-outputting unit outputs said status values delayed by a predetermined period of an operation clock from a timing of outputting said status values by said first signal-outputting unit during said test mode operation.
6. The semiconductor integrated circuit according to claim 1 , wherein said second signal-outputting unit outputs said status values delayed by a predetermined period of an operation clock from a timing of outputting said status values by said first signal-outputting unit during said test mode operation.