Semiconductor devices with rotated substrates and methods of manufacture thereof
View Patent ↗Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.
1. A semiconductor device, comprising:
a portion of a semiconductor wafer, the portion of the semiconductor wafer having a preferred crystalline plane direction; and
a plurality of devices formed over the portion of the semiconductor wafer, wherein a portion of the plurality of devices is formed within the semiconductor wafer, wherein the plurality of devices are oriented at an angle of between 5 and 40 degrees with respect to a direction parallel or perpendicular to the preferred crystalline plane direction of the portion of the semiconductor wafer.
2. The semiconductor device according to claim 1 , wherein the preferred crystalline plane direction comprises < 100 > or equivalent direction, or < 110 > or equivalent direction.
3. The semiconductor device according to claim 1 , wherein the plurality of devices comprise transistors.
4. The semiconductor device according to claim 3 , wherein each transistor comprises a source and a drain formed within a portion of the semiconductor wafer, a gate insulator disposed over the portion of the semiconductor wafer between the source and the drain, and a gate disposed over the gate insulator, wherein the source and drain of each transistor is joined in the direction of the angle of between 5 and 40 degrees with respect to the direction parallel or perpendicular to the preferred crystalline plane direction oft portion of the semiconductor wafer.
5. The semiconductor device according to claim 3 , further comprising a stress-inducing material layer disposed over at least a portion of the transistors.
6. The semiconductor device according to claim 5 , wherein the stress-inducing material comprises about 150 nm or less of silicon nitride.
7. The semiconductor device according to claim 3 , wherein the plurality of devices comprises complimentary metal oxide semiconductor (CMOS) devices, wherein each CMOS device comprises a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor.
8. The semiconductor device according to claim 7 , wherein the PMOS transistor, the NMOS transistor, or both. further includes a stress-inducing means.
9. The semiconductor device according to claim 8 , wherein the stress-inducing means comprises a stress-inducing material layer disposed over the PMOS transistor or the NMOS transistor.
10. The semiconductor device according to claim 8 , wherein each PMOS transistor and each NMOS transistor comprises a source and a drain formed within the portion of the semiconductor wafer, a gate insulator disposed over the portion of the semiconductor wafer between the source and the drain, and a gate disposed over the gate insulator, wherein the source and drain of each PMOS transistor and NMOS transistor is joined in the direction of the angle of between 5 and 40 degrees with respect to the direction parallel or perpendicular to the preferred crystalline plane direction of the portion of the semiconductor wafer, wherein the preferred crystalline plane direction comprises a cleavage direction of the semiconductor wafer.
11. The semiconductor device according to claim 8 , wherein the PMOS transistor but not the NMOS transistor includes a stress-inducing means.
12. The semiconductor device according to claim 8 , wherein the NMOS transistor but not the PMOS transistor includes a stress-inducing means.
13. The semiconductor device according to claim 8 , wherein both the PMOS transistor and the NMOS transistor include a stress-inducing means.
14. The semiconductor device according to claim 8 , wherein the stress-inducing means comprises a stress-inducing material layer disposed in a shallow trench isolation region proximate the PMOS transistor or the NMOS transistor.
15. The semiconductor device according to claim 8 , wherein the stress-inducing means comprises an epitaxially-formed lattice strained material forming a source, drain, or channel of the PMOS transistor or the NMOS transistor.
16. The semiconductor device according to claim 15 , wherein the epitaxially-formed lattice strained material comprises germanium or carbon containing silicon alloys.