IP Library Granted Patent US 7,369,835
Granted Patent B2
US 7,369,835 · App. 11/077,629 · Granted May 6, 2008

Image rejection mixer providing precision image rejection

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Quick Facts
Patent No.
US 7,369,835
App. No.
11/077,629
Granted
May 6, 2008
Kind
B2
Abstract

An image rejection mixer includes a first mixer, a second mixer, a first output adjust circuit, and a second output adjust circuit. The first mixer is coupled to receive an input RF signal and a local oscillator signal and includes a first mixer stage and a first output load stage. The second mixer is coupled to receive the input RF signal and a phase-converted local oscillator signal and includes a second mixer stage and a second output load stage. The first output adjust circuit is coupled to the first output load stage for modifying the signal waveform of a first output signal of the first mixer. The second output adjust circuit is coupled to the second output load stage for modifying the signal waveform of a second output signal of the second mixer. In this manner, the near-perfect image rejection result in the final IF signal can be obtained.

Claims (26)

1. An image rejection mixer comprising:

an input terminal for receiving an input radio frequency (RF) signal;

a first mixer coupled to receive said input RF signal and a signal from a local oscillator, said local oscillator providing a signal having a local oscillator frequency, said first mixer including a first mixer stage and a first output load stage and providing a first output signal;

a first phase converter coupled to convert a first phase of said signal from said local oscillator and to generate a phase-converted local oscillator signal;

a second mixer coupled to receive said input RF signal and said phase-converted local oscillator signal, said second mixer including a second mixer stage and a second output load stage and providing a second output signal;

a first output adjust circuit coupled to said first output load stage of said first mixer for modifying a signal waveform of said first output signal of said first mixer;

a second output adjust circuit coupled to said second output load stage of said second mixer for modifying a signal waveform of said second output signal of said second mixer;

a second phase converter coupled to convert a second phase of said second output signal of said second mixer and to generate a phase converted output signal; and

a combiner coupled to receive said first output signal and said phase converted output signal and combine said first output signal and said phase converted output signal to provide an output signal having an intermediate frequency,

wherein said first output adjust circuit and said second output adjust circuit operate to modify signal waveforms of said first output signal and said phase converted output signal so as to cancel nearly all signal components having an image frequency in said output signal having an intermediate frequency.

2. The image rejection mixer of claim 1 , wherein said each of said first and second output adjust circuits comprises one or more switchably connected passive electrical components, the one or more switchably connected passive electrical components being connected in parallel with each other and with the respective output load stage of the respective mixer and operative to modify the impedance of the respective output load stage of the respective mixer.

3. The image rejection mixer of claim 2 , wherein the one or more switchably connected passive electrical components comprises one or more switchably connected resistors.

4. The image rejection mixer of claim 3 , wherein the one or more switchably connected resistors comprises resistors having the same resistance values.

5. The image rejection mixer of claim 3 , wherein the one or more switchably connected resistors comprises resistors having different resistance values.

6. The image rejection mixer of claim 3 , wherein the one or more switchably connected capacitors comprises capacitors having the same capacitance values.

7. The image rejection mixer of claim 3 , wherein the one or more switchably connected capacitors comprises capacitors having different capacitance values.

8. The image rejection mixer of claim 2 , wherein the one or more switchably connected passive electrical components comprises one or more switchably connected capacitors.

9. The image rejection mixer of claim 1 , wherein said each of said first and second output adjust circuits comprises a low-pass filter coupled to receive the respective one of the first output signal of said first mixer and said phase converted output signal of said second mixer, the low-pass filter providing a filtered output signal to the combiner.

10. The image rejection mixer of claim 9 , wherein said low-pass filter comprises:

an input node receiving the respective one of the first output signal of said first mixer and said phase converted output signal of said second mixer;

a first resistor connected between said input node and an output node; and

one or more switchably connected passive electrical components connected in parallel between said output node and a power supply node.

11. The image rejection mixer of claim 10 , wherein the one or more switchably connected passive electrical components comprise one or more switchably connected resistors.

12. The image rejection mixer of claim 10 , wherein the one or more switchably connected passive electrical components comprise one or more switchably connected capacitors.

13. The image rejection mixer of claim 1 , wherein said first phase converter provides a 90° phase conversion and said second phase converter provides a −90° phase conversion.

14. The image rejection mixer of claim 1 , wherein said combiner comprises one of a summer and a subtractor.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2016
From: DORIS KAELIN, SOLELY IN HER CAPACITY AS DULY APPOINTED & ACTING CHAPTER 7 TRUSTEE OF THE BANKRUPTCY ESTATE OF CRESTA TECHNOLOGY CORPORATION, CHAPTER 7 CASE NO. 16-50808, PENDING IN U.S. BANKRUPTCY COURT FOR NO. DISTRICT OF CA, SAN JOSE DIV.
To: CF CRESPE LLC
Reel/Frame 038761/0663 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2016
From: DORIS KAELIN, SOLELY IN HER CAPACITY AS DULY APPOINTED & ACTING CHAPTER 7 TRUSTEE OF THE BANKRUPTCY ESTATE OF CRESTA TECHNOLOGY CORPORATION, CHAPTER 7 CASE NO. 16-50808, PENDING IN U.S. BANKRUPTCY COURT FOR NO. DIST OF CA, SAN JOSE DIVISION
To: CR CRESPE LLC
Reel/Frame 038741/0439 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2016
From: CRESTA TECHNOLOGY CORPORATION
To: CF CRESPE LLC
Reel/Frame 038709/0059 →
SECURITY INTEREST Recorded Dec 9, 2014
From: CRESTA TECHNOLOGY CORPORATION
To: CF DB EZ LLC
Reel/Frame 034564/0777 →
SECURITY AGREEMENT Recorded Feb 24, 2010
From: XCEIVE CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 023985/0281 →