Phase locked loop

1. A phase locked loop comprising:

an adjustable charge pump that generates a control voltage according to a control signal and a correction signal;

a voltage controlled oscillator that receives the control voltage and generates an output frequency according to the control voltage;

an analog to digital converter that receives the control voltage and generates a digital word therefrom;

a first register that receives and stores the digital word from the analog to digital converter;

a table memory that receives the digital word from the register and also receives a channel word and forms a table entry comprising an actual gradient from the digital word and the channel word;

an evaluation unit that receives the table entry from the table memory and generates a gradient error therefrom;

a second register that receives and stores the gradient error from the evaluation unit; and

a programmable current source that receives the gradient error from the second register and generates the correction signal according to the gradient error.

2. The phase locked loop of claim 1 , wherein the evaluation unit comprises a processing unit that calculates the gradient error.

3. The phase locked loop of claim 1 , further comprising a loop filter that filters the control voltage generated by the charge pump.

4. The phase locked loop of claim 1 , further comprising a phase/frequency detector that receives a reference frequency and a divided frequency and generates the control signal according to the reference frequency and the divided frequency.

5. The phase locked loop of claim 4 , further comprising a feedback path comprising a frequency divider that divides the output frequency to generate the divided frequency.

6. The phase locked loop of claim 5 , wherein the phase frequency detector generates the control signal when the divided frequency differs from the reference frequency.

7. The phase locked loop of claim 5 , further comprising a sigma delta modulator that sets a frequency division value on the frequency divider.

8. The phase locked loop of claim 7 , wherein the sigma delta modulator sets the frequency division value according to the channel word and a digital data signal.

9. A phase locked loop comprising:

a phase/frequency detector that generates a control signal according to reference frequencies and divided frequencies;

an adjustable charge pump that generates control voltages according to the control signal and a correction signal;

a voltage controlled oscillator that receives the control voltages and generates an output frequencies according to the control voltages;

an analog to digital converter that receives the control voltages and generates digital words therefrom;

a first register that receives and stores the digital words from the analog to digital converter;

a table memory that receives the digital words from the register and also receives channel word and forms table entries comprising actual gradients according to the respective digital words and the channel words over a plurality of frequency channels;

an evaluation unit that receives the table entries from the table memory and generates gradient errors and a delta error over the plurality of frequency channels;

a second register that receives and stores the delta error from the evaluation unit; and

a programmable current source that receives the delta error from the second register and generates the correction signal according to the delta error.

10. The phase locked loop of claim 9 , wherein the programmable current source has a resolution of 9 bits.

11. The phase locked loop of claim 9 , wherein the evaluation unit determines tuning gradients from the channel words that correspond to the plurality of frequency channels and generates the delta error at least partially according to the tuning gradients.

12. The phase locked loop of claim 9 , further comprising a feedback path comprising a frequency divider that divides the output frequencies to generate the divided frequencies.

13. The phase locked loop of claim 12 , further comprising a sigma delta modulator that sets a frequency division value on the frequency divider.

14. A method of operating a phased locked loop comprising:

generating a control voltage according to a control signal and a correction signal;

generating an output frequency according to the control voltage;

obtaining a digital word from the control voltage;

determining an actual gradient at least partially according to the digital word and a channel word using a table memory;

generating a gradient error at least partially according to the actual gradient and a nominal gradient; and

generating the correction signal according to the gradient error.

15. The method of claim 14 , generating the correction signal is performed by a programmable current source.

16. The method of claim 14 , further comprising low-pass filtering the control voltage prior to generating the output frequency.

17. The method of claim 14 , further comprising generating a divided frequency by dividing the output frequency by a division value.

18. The method of claim 17 , further comprising generating the control signal by comparing frequency values of the reference frequency and the divided frequency.

19. The phase locked loop of claim 1 , wherein the evaluation unit further generates the gradient error based on the actual gradient and a nominal gradient.

20. The phase locked loop of claim 9 , wherein the evaluation unit generates the gradient errors based on the actual gradients and on nominal gradients over a plurality of frequemcy channels.