IP Library Granted Patent US 7,268,527
Granted Patent B2
US 7,268,527 · App. 11/078,034 · Granted Sep 11, 2007

Method and apparatus for determining load current in a CPU core voltage regulator

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Quick Facts
Patent No.
US 7,268,527
App. No.
11/078,034
Granted
Sep 11, 2007
Kind
B2
Abstract

An apparatus and method for measuring output current and power in real-time is provided for a CPU core powered by a DC-to-DC power converter having active voltage positioning. In an embodiment of the invention, a switched mode power converter comprises at least one power switch operatively coupled to an input voltage source, an output filter operatively coupled to the at least one power switch to provide an output voltage and output current to a load, and a control circuit coupled to the at least one power switch. The control circuit activates the power switch with a duty cycle controlled to regulate at least one of the output voltage and the output current. The control circuit receives a first control signal defining a desired value for the output voltage, a second control signal defining a relationship between voltage input and current draw for the load, and a voltage sense signal corresponding to an actual value of the output voltage. The control circuit thereby provides a measurement of load current.

Claims (35)

1. A switched mode power converter, comprising:

at least one power switch operatively coupled to an input voltage source;

an output filter operatively coupled to said at least one power switch to provide an output voltage and output current to a load;

a control circuit coupled to said at least one power switch, said control circuit activating said at least one power switch with a duty cycle controlled to regulate at least one of said output voltage and said output current, said control circuit receiving a first control signal defining a desired value for said output voltage, a second control signal defining a relationship between voltage input and current draw for said load, and a voltage sense signal corresponding to an actual value of said output voltage, said control circuit thereby providing a measurement of load current therefrom.

2. The switched mode power converter of claim 1 , wherein said first control signal further comprises a digital signal.

3. The switched mode power converter of claim 2 , wherein said first control signal further comprises a voltage identification (VID) code.

4. The switched mode power converter of claim 2 , wherein said control circuit further comprises a digital-to-analog converter receiving said first control signal and providing a corresponding voltage.

5. The switched mode power converter of claim 1 , wherein said second control signal further comprises a load-line signal.

6. The switched mode power converter of claim 1 , wherein said control circuit provides said measurement of load current in accordance with the following equation:

I LOAD =( V DAC −V OUT )/ AVP SLOPE

wherein, V DAC is an analog voltage corresponding to the first control signal, V OUT is the voltage sense signal, AVP SLOPE is the slope of the second control signal, and I LOAD is the load current.

7. The switched mode power converter of claim 1 , wherein said control circuit further receives a current droop signal corresponding to changes in said output current.

8. The switched mode power converter of claim 7 , further comprising a current sensor operatively coupled to said output filter, said current sensor providing said current droop signal.

9. The switched mode power converter of claim 1 , wherein said control circuit further comprises a data in/out port adapted to receive at least said second control signal and send at least said output current measurement.

10. The switched mode power converter of claim 1 , wherein said load further comprises a microprocessor.

11. The switched mode power converter of claim 1 , wherein said at least one power switch further comprises a high-side power switch and a low-side power switch.

12. A control circuit for use in a switched mode power converter including at least one power switch operatively coupled to an input voltage source, an output filter operatively coupled to said at least one power switch to provide an output voltage and output current to a load, said control circuit adapted to be operatively coupled to said at least one power switch, said control circuit activating said at least one power switch with a duty cycle controlled to regulate at least one of said output voltage and said output current, said control circuit receiving a first control signal defining a desired value for said output voltage, a second control signal defining a relationship between voltage input and current draw for said load, and a voltage sense signal corresponding to an actual value of said output voltage, said control circuit thereby providing a measurement of load current therefrom.

13. The control circuit of claim 12 , wherein said first control signal further comprises a digital signal.

14. The control circuit of claim 13 , wherein said first control signal further comprises a voltage identification (VID) code.

15. The control circuit of claim 13 , further comprising a digital-to-analog converter receiving said first control signal and providing a corresponding voltage.

16. The control circuit of claim 12 , wherein said second control signal further comprises a load-line signal.

17. The control circuit of claim 12 , wherein said measurement of load current is derived in accordance with the following equation:

I LOAD =( V DAC −V OUT )/ AVP SLOPE

wherein, V DAC is an analog voltage corresponding to the first control signal, V OUT is the voltage sense signal, AVP SLOPE is the slope of the second control signal, and I LOAD is the load current.

18. The control circuit of claim 12 , further comprising a data in/out port adapted to receive at least said second control signal and send at least said output current measurement.

19. A method for monitoring load current drawn by a microprocessor, comprising the steps of:

providing a regulated output voltage and output current to the microprocessor;

receiving a first control signal defining a desired value for said output voltage, a second control signal defining a relationship between voltage input and current drawn by said microprocessor, and a voltage sense signal corresponding to an actual value of said output voltage; and

deriving the microprocessor load current in accordance with the following equation:

I LOAD =( V DAC −V OUT )/ AVP SLOPE

wherein, V DAC is an analog voltage corresponding to the first control signal, V OUT is the voltage sense signal, AVP SLOPE is the slope of the second control signal, and I LOAD is the load current.

20. The method of claim 19 , wherein said first control signal further comprises a digital signal.

21. The method of claim 20 , wherein said first control signal further comprises a voltage identification (VID) code.

22. The method of claim 2 , further comprising converting said first control signal to a corresponding analog voltage.

23. The method of claim 19 , wherein said second control signal further comprises a load-line signal.

Assignments (6)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (040646/0799) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0544 →
SECURITY INTEREST Recorded Nov 17, 2016
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 040646/0799 →
RELEASE OF SECURITY INTEREST Recorded May 2, 2013
From: JEFFERIES FINANCE LLC
To: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.
Reel/Frame 030341/0059 →
SECURITY AGREEMENT Recorded May 2, 2013
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 030341/0099 →
GRANT OF SECURITY INTEREST Recorded Mar 20, 2012
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 027897/0141 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2007
From: HORNER, JON
To: SEMTECH CORPORATION
Reel/Frame 019585/0971 →