Semiconductor device and method for manufacturing same
View Patent ↗There is provided a technique for obtaining improved maximum allowed value for the antenna ratio while inhibiting the damage on the gate insulating film of the MOSFET. A semiconductor device having a configuration that comprises a silicon substrate, a contact interlayer film, a first interconnect interlayer film, a first via interlayer film and a second interconnect interlayer film, all of which are sequentially formed in this order, comprises two protective diodes, which are coupled to a MOSFET via the second interconnect.
1. A semiconductor device, comprising:
a semiconductor substrate;
a MOSFET that is provided on a main face of said semiconductor substrate;
a protective diode that is coupled to a gate electrode of said MOSFET through an interconnect;
a transistor coupling plug that is in contact with said gate electrode on a bottom surface of said transistor coupling plug; and
a protective plug that is in contact with said protective diode on a bottom surface of said protective plug and in connect with said gate electrode;
wherein bottom surface area of said protective plug is larger than bottom surface area of said transistor coupling plug.
2. The semiconductor device according to claim 1 , wherein at least one of said protective diode having a plurality of protective diodes.
3. The semiconductor device according to claim 1 , wherein at least one of said protective diode contacting a plurality of protective plugs.
4. The semiconductor device according to claim 1 , wherein said protective diode that is coupled to said gate electrode includes a diffusion layer provided on said semiconductor substrate; said protective plug that is in contact with said diffusion layer on a bottom surface of said protective plug, and wherein bottom surface area of said protective plug is larger than bottom surface area of said transistor coupling plug.
5. The semiconductor device according to claim 1 , said MOSFET which is provided on a main face of said semiconductor substrate and has an antenna ratio of not lower than 10,000.
6. The semiconductor device according to claim 1 , wherein a plurality of said protective diode is disposed at predetermined intervals.
7. The semiconductor device according to claim 1 , wherein a plurality of said protective diode is arranged to form an array pattern.
8. The semiconductor device according to claim 1 , wherein said protective diode is provided within an internal circuit.
9. The semiconductor device according to claim 1 , wherein said protective diode is disposed adjacent to said MOSFET via an isolation region.
10. The semiconductor device according to claim 1 , wherein said interconnect is coupled to said protective diode via the protective plug,
wherein maximum allowed value R max of antenna ratio R of said MOSFET is established in accordance with bottom surface area S CT of said protective plug, and
wherein said maximum allowed value R max , is presented by Equation (1):
R max =5.0×10 5 (1/μm 2 ) S CT +5000 (1)
11. A method for manufacturing the semiconductor device, comprising:
forming a MOSFET and a protective diode on a main face of a silicon substrate;
embedding a transistor coupling plug and a protective plug within an insulating film, said transistor coupling plug being coupled to a gate electrode of said MOSFET and said protective plug being coupled to a diffusion layer of said protective diode;
forming an interconnect within said insulating film, said interconnect being coupled to said transistor coupling plug and said protective plug; and
determining an upper limit of antenna ratio of said interconnect coupled to said transistor coupling plug by a contacting area of said protective plug being in contact with said diffusion layer of said protective diode,
wherein said interconnect is formed in said forming said interconnect so that the formed interconnect provides said antenna ratio that is equal to or lower than said upper limit determined in said determining said upper limit of said antenna ratio.