Semiconductor device and test method for the same
View Patent ↗A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW 0 -SW 4 connected between input/output pads P 0 -P 4 and a testing line L 0 so that pads in an arbitrary combination, among the off-probe pads P 1 -P 4 that are not made in contact with the tester probe Pr 0 , are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P 0 that is made in contact with the tester probe Pr 0 , and the leak current of the probes is measured with the tester TS.
1. A semiconductor device chip capable of testing, the semiconductor device chip comprising:
switch elements which are turned on by a switch control signal which becomes active at the time of testing; and
common testing lines, each of which is connected to either input pads or output pads through the switch elements, wherein every other input/output pad among the input/output pads in linear alignment is connected to different common testing lines than the other of the every other input/output pads, and when one of the input pads or the output pads connected to each common testing line is connected to a different tester probe, different biases are applied between adjacent input/output pads and a number of input/output pads is compressed at the time of testing.
2. A semiconductor device chip capable of testing, the semiconductor device chip comprising:
switch elements which are turned on by a switch control signal which becomes active at the time of testing; and
common testing lines, each of which is connected to either input pads or output pads through the switch elements, wherein each of the common testing lines is connected to one or more input/output pad and adjacent input/output pads are connected to different common testing lines, and when one of the input pads or the output pads connected to each common testing line is connected to a different tester probe, different biases are applied between adjacent input/output pads and a number of input/output pads is compressed at the time of testing.
3. A semiconductor device chip according to claim 2 , wherein each of the switch elements is formed of a transfer gate which is made conductive in response to each of the switch control signals.
4. A semiconductor device chip according to claim 2 , wherein the switch control signal is supplied from the internal circuit at time of testing.
5. A semiconductor device according to claim 2 , wherein the switch control signal is supplied as a high-level signal through a switch control pad, the switch control pad being connected to the low-level power voltage through a resistor.
6. A semiconductor device according to claim 2 , wherein the switch control signal is supplied as a low-level signal through a switch control pad, the switch control pad being connected to the high-level power voltage through a resistor.
7. A semiconductor device according to claim 2 , wherein the switch control signal is generated by a switch control signal generation circuit.
8. A semiconductor device according to claim 7 , wherein the switch control signal generation circuit generates the switch control signal based on the cutting of a fuse.
9. A semiconductor device according to claim 2 , wherein each of the common testing lines has voltage setting unit.
10. A semiconductor device according to claim 9 , wherein the voltage setting unit comprises a logic inverter which connects a pair of the common testing lines.
11. A semiconductor device according to claim 9 , wherein the voltage setting unit comprises a switch element which connects one of a pair of the common testing lines to the low-level power voltage in response to the switch control signal.
12. A semiconductor device according to claim 9 , wherein the voltage setting unit comprises a switch element which connects one of a pair of the common testing lines to the high-level power voltage in response to the switch control signal.
13. A semiconductor device wafer in which a plurality of semiconductor device chips are arranged, the semiconductor device chip comprising:
switch elements which are turned on by a switch control signal which becomes active at the time of testing; and
common testing lines, each of which is connected to either input pads or output pads through the switch elements, wherein each of the common testing lines is connected to one or more input/output pad and adjacent input/output pads are connected to different common testing lines, and when one of the input pads or the output pads connected to each common testing line is connected to a different tester probe, different biases are applied between adjacent input/output pads and a number of input/out pads is compressed at the time of testing.
14. A semiconductor device wafer in which a plurality of semiconductor device chips are arranged, the semiconductor device chip comprising:
switch elements which are turned on by a switch control signal which becomes active at the time of testing; and
common testing lines each of which is connected to either input pads or output pads through the switch elements, wherein every other input/output pad among the input/output pads in linear alignment is connected to different common testing lines than the other of the every other input/output pads, and when one of the input pads or the output pads connected to each common testing line is connected to a different tester probe, different biases are applied between adjacent input/output pads and a number of input/output pads is compressed at the time of testing.