Crossbar switch debugging
View Patent ↗A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.
1. A crossbar switch comprising:
a plurality of input/output (I/O) ports;
a debug block for storing chip status information;
a control register storing configuration data for the I/O ports, said configuration data assigning each said I/O port to function as either a crossbar port or a debug port;
a crossbar switch interconnect fabric coupleable to said plurality of I/O ports for use in communication between a number of said I/O ports presently assigned to function as crossbar ports according to said configuration data; and
a debug bus coupled to said debug block and to each said I/O port, for outputting said status information stored in said debug block via one of said I/O port presently assigned to function as said debug port according to said configuration data.
2. The crossbar switch as set forth in claim 1 , wherein said plurality of ports comprises eight ports.
3. The crossbar switch as set forth in claim 1 , wherein said switch resides on an ASIC.
4. The crossbar switch as set forth in claim 1 , wherein said plurality of ports are serial ports.
5. The crossbar switch as set forth in claim 1 , wherein the data stored in the control register can be changed to change an assignment of at least one said I/O port.
6. A system comprising:
a crossbar having a plurality of I/O ports; a debug block residing in said crossbar;
a control register residing in said crossbar, said control register storing configuration data for the I/O ports, said configuration data assigning each said I/O port to function as either a crossbar port or a debug port;
a crossbar switch interconnect fabric coupleable to said plurality of I/O ports for use in communication between a number of said I/O ports presently assigned to function as crossbar ports according to said configuration data; and
a debug bus coupled to said debug block and to each said I/O port, wherein status information is stored in said debug block and communicated via said debug bus from said debug block to one of said I/O port presently assigned to function as said debug port according to said configuration data.
7. The system as set forth in claim 6 wherein said status information is output in accordance with the SERDES protocol.
8. The system as set forth in claim 6 further comprising a logic analyzer coupled to said selected port for analyzing said status information.
9. The system as set forth in claim 6 , wherein the data stored in the control register is alterable.
10. A method for debugging a crossbar device having a crossbar switch interconnect fabric and a plurality of input/output (I/O) ports comprising:
storing configuration data for the I/O ports in a control register, said configuration data assigning each said I/O port to function as either a crossbar port or a debug port;
storing status information for said crossbar device in a debug block of the crossbar device;
communicating the status information via a debug bus from the debug block to one of a said selected I/O port presently assigned to function as said debug port according to said configuration data and
outputting said status information via said selected I/O port presently assigned to function as said debug port according to said configuration data.
11. The method as set forth in claim 10 , wherein said status information is output as serial data.
12. The method as set forth in claim 11 , wherein said serial data is in accordance with the SERDES protocol.
13. The method as set forth in claim 10 , wherein the crossbar device is in an ASIC.
14. The method as set forth in claim 10 , further comprising: reading said information from said debug block through said selected port.