PIN photodiode structure and fabrication process for reducing dielectric delamination
View Patent ↗A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.
1. A PIN photodiode comprising:
a substrate;
a first type electrode layer disposed on the substrate;
an intrinsic layer, including a first lower region having a first length, and a second upper region having a second length, smaller than the first length, disposed over a portion of the first type electrode layer with a step change from the first length to the second length located at a junction between said first lower region and said second upper region;
a second type electrode layer disposed over at least a portion of the intrinsic layer so as to form a mesa shaped structure; and
a passivation layer disposed over the mesa shaped structure.
2. A photodiode as defined in claim 1 , wherein said lower and upper regions are substantially circular in shape.
3. A photodiode as defined in claim 1 , wherein said lower and upper regions are annular regions.
4. A photodiode as defined in claim 1 , wherein said second type electrode layer is disposed over substantially the entire upper surface of said upper region.
5. A photodiode as defined in claim 1 , further comprising a contact layer disposed over a portion of said first type electrode layer.
6. A PIN photodiode comprising:
a semi-insulating substrate;
an n-type electrode layer disposed on the substrate;
an intrinsic layer, including a first lower region having a first lateral length, and a second upper region having a second lateral length, smaller than the first length, said intrinsic layer being disposed over a portion of the n-type eletrode layer with a step change from the first length to the second length located at a junction between said first lower region and said second upper region;
a p-type electrode layer disposed over at least a portion of the intrinsic layer; and
a passivation layer disposed over the p-type electrode layer, the intrinsic layer, and the n-type electrode layer.
7. A vertical PIN photodiode comprising:
a substrate;
a first type electrode layer disposed on the substrate;
an intrinsic layer disposed on the first type electrode layer;
a second type electrode layer disposed over the intrinsic layer;
a trench etched through the electrode and intrinsic layers into the substrate;
a layer of passivation material disposed over the second type electrode layer and in the trench.
8. The photodiode as defined in claim 7 , wherein the passivation material is composed of polyimide.