IP Library Patent Application 11080511
Patent Application
App. No. 11/080,511

Photomask and pattern forming method employing the same

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
11/080,511
Abstract

A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.

Claims (16)

1 - 9 . (canceled)

10 . A method of manufacturing a dynamic random access memory, comprising the steps of:

preparing a phase shifting mask including (a) an element forming area having a semitransparent phase shifting film, and (b) a light shielding area provided at a peripheral edge of said element forming area and serving to make an intensity of light having passed through said light shielding area smaller than an intensity of light having passed through said semitransparent phase shifting film, as measured on a to-be-exposed photoresist film, and

transferring a hole pattern formed at said element forming area of said phase shifting mask onto said photoresist film, by using a projection exposure apparatus.

11 . A method for manufacturing a dynamic random access memory according to claim 10 , wherein said light shielding area includes a semitransparent phase shifting pattern having a semitransparent phase shifting portion and a transparent portion.

12 . A method for manufacturing a dynamic random access memory according to claim 11 , wherein a ratio a of an area of said transparent portion to an area of said phase shifting portion is defined by a α=β{square root}T, where T is the transmittance of said semitransparent phase shifting portion, and β is a value falling within a range of 0.5≦β≦2.0.

13 . A method for manufacturing a dynamic random access memory according to claim 10 , wherein said peripheral edge is double-exposed in said transferring step.

14 . A method for manufacturing a dynamic random access memory according to claim 10 , wherein an alignment pattern is provided at said peripheral edge.

15 . A method for manufacturing a dynamic random access memory, comprising the steps of:

preparing a phase shifting mask including (a) an element forming area having a first semitransparent phase shifting film having a transmittance to exposure light of not more than 25%, and (b) a light shielding area provided at a peripheral edge of said element forming area and serving to make an intensity of light having passed through said light shielding area smaller than an intensity of light having passed through said semitransparent phase shifting film, as measured on a to-be-exposed photoresist film,

preparing a semiconductor substrate on which said to-be-exposed photoresist film is formed, and

transferring a hole pattern formed at said element forming area of said phase shifting mask onto said photoresist film by using a projection exposure apparatus.

16 . A method for manufacturing a dynamic random access memory according to claim 15 , wherein said light shielding area includes a semitransparent phase shifting pattern having a semitransparent phase shifting portion and a transparent portion.

17 . A method for manufacturing a dynamic random access memory according to claim 16 , wherein a ratio α of an area of said transparent portion to an area of said phase shifting portion is defined by α=β{square root}T, where T is the transmittance of said semitransparent phase shifting portion, and β is a value falling within a range of 0.5 ≦β≦2.0.

18 . A method for manufacturing a dynamic random access memory according to claim 15 , wherein said peripheral edge is double-exposed in said transferring step.

19 . A method for manufacturing a dynamic random access memory according to claim 15 , wherein an alignment pattern is provided at said peripheral edge.