Jitter detection circuit

1. The jitter detection circuit of a phase locked loop circuit, comprising:

a comparison circuit that compares an input clock that is inputted to the phase locked loop circuit and an output clock that is outputted by the phase locked loop circuit and which, when the frequency difference between the input clock and the output clock is outside a predetermined range, outputs a first anomaly signal,

wherein the comparison circuit is constituted as a digital circuit, and

wherein the comparison circuit counts the number of pulses of the output clock in a reference time corresponding to m-multiplied cycle (m is a natural number) of the input clock and determines whether the frequency difference is outside the predetermined range on the basis of the count value.

2. The jitter detection circuit according to claim 1 , wherein the count value is expressed by using a plurality of bits; and

the comparison circuit performs the determination based on only some of the bits of the plurality of bits.

3. The jitter detection circuit according to claim 1 , wherein the comparison circuit comprises a counter that counts the number of pulses of the output clock; and

the counter resets the count value when the input clock is inputted directly or via a divider.

4. The jitter detection circuit according to claim 3 , wherein the comparison circuit outputs a second anomaly signal when the count number of the counter is equal to or more than a predetermined value without resetting the count value.

5. The jitter detection circuit of a phase locked loop circuit according to claim 4 , wherein the comparison circuit outputs a third anomaly signal when the count value has not changed once in the reference time.

6. The jitter detection circuit of a phase locked loop circuit according to claim 1 , wherein the comparison circuit outputs a third anomaly signal when the count value has not changed once in the reference time.

7. The jitter detection circuit of a phase locked loop circuit comprising:

a comparison circuit that compares an input clock that is inputted to the phase locked loop circuit and an output clock that is outputted by the phase locked loop circuit and which, when the frequency difference between the input clock and the output clock is outside a predetermined range, outputs a first anomaly signal,

wherein the comparison circuit is constituted as a digital circuit; and

a switching circuit which receives a plurality of clocks including the output clock and outputs any one clock among the plurality of clocks,

wherein the switching circuit selects and, outputs a clock excluding the output clock when the first anomaly signal is outputted by the comparison circuit.

8. The jitter detection circuit of a phase locked loop circuit according to claim 7 , comprising:

a divider circuit that multiplies the cycle of the input clock by m (m is a natural number);

a counter which inputs the input clock multiplied by m that is outputted by the divider circuit and the output clock and counts the number of pulses of the output clock in a reference time that is determined based on the input clock multiplied by m; and

a comparator that determines whether the frequency difference is outside the predetermined range on the basis of the count value of the counter.