Thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer; forming a semiconductor layer; forming a lower data line; forming an upper data line including a source electrode and a drain electrode, the upper data line including a portion disposed on the semiconductor layer without interposing the lower data line; forming a passivation layer having a first contact hole exposing the drain electrode at least in part; and forming a pixel electrode on the first contact hole to contact the drain electrode.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on a substrate;
forming a gate insulating layer;
forming a semiconductor layer;
forming a lower data line;
forming an upper data line including a source electrode and a drain electrode, the upper data line including a portion disposed on the semiconductor layer without interposing the lower data line;
forming a passivation layer having a first contact hole exposing the drain electrode at least in part; and
forming a pixel electrode on the first contact hole to contact the drain electrode.
2. The method of claim 1 , wherein the upper data line has a contact characteristic with the pixel electrode better than the lower data line.
3. The method of claim 1 , wherein the lower data line comprises Al or Al alloy.
4. The method of claim 3 , wherein the upper data line comprises Cr, Mo, or Mo alloy.
5. The method of claim 4 , wherein the pixel electrode comprises indium tin oxide (ITO) or indium zinc oxide (IZO).
6. The method of claim 1 , wherein the upper data line caps the lower data line.
7. The method of claim 6 , wherein the source electrode or the drain electrode is formed by the upper data line only.
8. The method of claim 1 , further comprising:
forming an ohmic contact layer on the semiconductor layer.
9. The method of claim 8 , wherein the formation of the gate insulating layer, the formation of the semiconductor layer, the formation of the ohmic contact layer, and the formation of the lower data line comprises:
depositing the gate insulating layer, the semiconductor layer, the ohmic contact layer, and a lower conductive film in sequence;
forming a first photoresist on the lower conductive film;
sequentially etching the lower conductive film, the ohmic contact layer, and the semiconductor layer using the first photoresist as an etch mask;
deforming the first photoresist to form a second photoresist; and
etching the lower conductive film to form the lower data line.
10. The method of claim 9 , wherein the first photoresist has a position-dependent thickness.
11. The method of claim 10 , wherein the first photoresist is formed by using a mask having a transparent area, an opaque area, and a translucent area.
12. The method of claim 11 , wherein the deformation of the first photoresist comprises:
ashing the first photoresist.
13. The method of claim 12 , wherein the ashing of the first photoresist comprises:
removing a portion of the first photoresist corresponding to the translucent area of the mask.
14. The method of claim 1 , further comprising:
forming a second contact hole at the passivation layer or the gate insulating layer exposing a portion of the gate line or the data line; and
forming a contact assistant on the second contact hole to contact the exposed portion of the gate line or the data line.