Delay equalized Z/2Z ladder for digital to analog conversion

1. An impedance ladder circuit, comprising:

a series connection of n first resistors each having a resistance R, each adjacent pair of the first resistors defining an intermediate node there between, the series of n first resistors defining an output node at a first end and a termination node at a second end;

n second resistors each having a resistance substantially equal to kR, where k is a real number, each second resistor coupled between a respective one of the intermediate nodes and a reference and between the termination node and the reference;

a termination resistor substantially equal to

(

1

+

1

+

4

⁢

k

2

)

·

R

wherein k does not equal 2, and wherein the termination resistor is coupled between the termination node and the reference in parallel with one of the second resistors; and

n capacitors, each coupled in parallel with a respective one of the first resistors.

2. The circuit according to claim 1 , wherein each intermediate node and the termination node has a parasitic capacitance C p , and wherein each of the n capacitors have a capacitance substantially equal to kC p .

3. The circuit according to claim 1 , further comprising n switches, each switch coupled between a respective one of the intermediate nodes and a corresponding current source, and between the termination node and a corresponding current source.

4. The circuit according to claim 3 , wherein the switches are controlled by digital bits.

5. The circuit according to claim 1 , further comprising a load resistance coupled between the output node and the reference.

6. The circuit according to claim 1 , further comprising n+1 switches, each coupled between a respective one of the nodes and a respective current source, each said switch controlled by a corresponding digital bit, whereby the termination node switch is controlled by a least significant bit and the output node switch is controlled by a more significant bit.

7. The circuit according to claim 6 , wherein each intermediate node has an associated capacitance C p , the termination node has a capacitance substantially equal to 2C p ; and each of the n capacitors have a capacitance substantially equal to 2C p .

8. The circuit according to claim 6 , wherein the n+1 switches are controlled by digital bits.

9. The circuit according to claim 6 , further comprising:

a load resistance coupled between the output node and the reference; and

one or more additional switches, each coupled between the output node and a respective current source.

10. The circuit according to claim 9 , wherein the additional switches are controlled by a thermometer code generated from most significant bits.

11. An impedance ladder, comprising:

a first R/kR ladder network;

capacitors coupled across series resistors within the R/kR ladder network,

wherein the capacitors are sized to substantially match delays from parasitic capacitances associated with parallel resistors of the R/kR ladder network, and

wherein k is a real number; and

a second R/kR ladder configured substantially similar to the first R/kR ladder,

wherein the first and second R/kR ladders are coupled together by differentially controlled switches.

12. The impedance ladder according to claim 11 , wherein nodes within the R/kR ladder network include parasitic capacitances, wherein each of the capacitors is substantially equal to twice the parasitic capacitances of a corresponding node.

13. The impedance ladder according to claim 12 , wherein resistors within the R/kR ladder network comprise poly resistors.

14. The impedance ladder according to claim 13 , wherein the capacitors comprise metal finger capacitors.

15. The impedance ladder according to claim 14 , wherein the metal finger capacitors are fabricated on top of the poly resistors.