IP Library Granted Patent US 7,512,175
Granted Patent B2
US 7,512,175 · App. 11/081,267 · Granted Mar 31, 2009

Method for synchronizing exporter and exciter clocks

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,512,175
App. No.
11/081,267
Granted
Mar 31, 2009
Kind
B2
Abstract

A method for synchronizing an exciter clock with a modem frame clock in a broadcasting system comprises the steps of receiving a plurality of modem frame pulses that are representative of the start of modem frames of audio signals and data signals, wherein timing of the modem frame pulses is controlled by a modem frame clock, producing an exciter clock signal, counting pulses representative of the exciter clock signal to produce a count representative of timing error of each incoming modem frame pulse, and controlling the exciter clock signal in response to the count. An apparatus that performs the method is also provided.

Claims (38)

1. A method for synchronizing an exciter clock with a modem frame clock in a broadcasting system, the method comprising the steps of:

using a first input to receive a plurality of modem frame pulses that are representative of the start of modem frames, wherein timing of the modem frame pulses is controlled by a modem frame clock;

using a clock to produce an exciter clock signal;

using a counter to count pulses representative of the exciter clock signal to produce a count representative of timing error of each incoming modem frame pulse;

using a loop filter to control the exciter clock signal in response to the count; and

using a second input to reset the count in response to a combination of a sync signal and the modem frame pulses.

2. The method of claim 1 , further comprising the step of:

using a latch to latch the count in response to the modem frame pulses.

3. The method of claim 1 , further comprising the step of:

using a processor to take the 2's complement of the count.

4. The method of claim 1 , wherein pulses representative of the exciter clock signal are produced using a variable-modulus divider.

5. The method of claim 1 , wherein the frequency of the modem frame pulses is about 0.673 Hz, and the frequency of the exciter clock is about 10 MHz.

6. An apparatus for synchronizing an exciter clock with a modem frame clock in a broadcasting system, the apparatus comprising:

an input for receiving a plurality of modem frame pulses that are representative of the start of modem frames, wherein timing of the modem frame pulses is controlled by a modem frame clock;

a voltage controlled oscillator for producing an exciter clock signal;

a counter for counting pulses representative of the exciter clock signal to produce a count representative of timing error of each incoming modem frame pulse;

a loop filer for controlling the exciter clock signal in response to the count; and

an input for resetting the count in response to a combination of a sync signal and the modem frame pulses.

7. The apparatus of claim 6 , further comprising:

a latch for latching the count in response to the modem frame pulses.

8. The apparatus of claim 6 , further comprising:

a circuit for taking the 2's complement of the count.

9. The apparatus of claim 6 , further comprising:

a variable-modulus divider for producing pulses representative of the exciter clock signal.

10. The apparatus of claim 6 , wherein the frequency of the modem frame pulses is about 0.673 Hz, and the frequency of the exciter clock is about 10 MHz.

11. An apparatus for synchronizing an exciter clock with a modem frame clock in a broadcasting system, the apparatus comprising:

means for receiving a plurality of modem frame pulses that are representative of the start of modem frames, wherein timing of the modem frame pulses is controlled by a modem frame clock;

means for producing an exciter clock signal;

means for counting pulses representative of the exciter clock signal to produce a count representative of timing error of each incoming modem frame pulse;

means for controlling the exciter clock signal in response to the count; and

means for resetting the count in response to a combination of a sync signal and the modem frame pulses.

12. The apparatus of claim 11 , further comprising:

means for latching the count in response to the modem frame pulses.

13. The apparatus of claim 11 , further comprising:

means for taking the 2's complement of the count.

14. The apparatus of claim 11 , further comprising:

means for producing pulses representative of the exciter clock signal.

15. The apparatus of claim 11 , wherein the frequency of the modem frame pulses is about 0.673 Hz, and the frequency of the exciter clock is about 10 MHz.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Oct 27, 2022
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: VEVEO LLC (F.K.A. VEVEO, INC.); DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 061786/0675 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
RELEASE OF SECURITY INTEREST Recorded Dec 6, 2016
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: IBIQUITY DIGITAL CORPORATION
Reel/Frame 040821/0108 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
SECURITY INTEREST Recorded Nov 9, 2015
From: IBIQUITY DIGITAL CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 037069/0153 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2015
From: MERRILL LYNCH CREDIT PRODUCTS, LLC
To: IBIQUITY DIGITAL CORPORATION
Reel/Frame 036877/0146 →
PATENT SECURITY AGREEMENT SUPPLEMENT Recorded Jul 21, 2009
From: IBIQUITY DIGITAL CORPORATION
To: MERRILL LYNCH CREDIT PRODUCTS, LLC, AS COLLATERAL AGENT
Reel/Frame 022980/0032 →
PATENT SECURITY AGREEMENT Recorded Dec 11, 2006
From: IBIQUITY DIGITAL CORPORATION
To: MERRILL LYNCH CREDIT PRODUCTS, LLC, AS ADMINISTRATIVE AND COLLATERAL AGENT
Reel/Frame 018606/0578 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2005
From: KROEGER, BRIAN WILLIAM
To: IBIQUITY DIGITAL CORPORATION
Reel/Frame 016393/0034 →