IP Library Granted Patent US 8,018,927
Granted Patent B2
US 8,018,927 · App. 11/081,514 · Granted Sep 13, 2011

Network element with multistage lower order switching matrix

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Quick Facts
Patent No.
US 8,018,927
App. No.
11/081,514
Granted
Sep 13, 2011
Kind
B2
Abstract

A network element for a transport network contains a multistage lower order switching matrix with at least an input matrix stage and an output matrix stage designed to switch lower order multiplex units and with a center stage capable of switching higher order multiplex units, only, thereby connecting the input and output stages.

Claims (27)

1. A network element for a transport network designed for the transport of framed multiplex signals comprising higher order multiplex units capable of carrying lower order multiplex units, the network element comprising:

a multistage lower order switch matrix wherein said lower order switch matrix comprises:

at least an input matrix stage and an output matrix stage which are both designed to switch said lower order multiplex units, and

a center stage capable of only switching higher order multiplex units; and

input/output ports which receive and transmit the framed multiplex signals comprising frames carrying the higher order multiplexing units, wherein each higher order multiplexing unit is capable of carrying lower order multiplexing units.

2. A network element according to claim 1 , wherein said lower order multiplex units are addressed inside said higher order multiplex units by tributary unit pointers and wherein said network element comprises tributary unit pointer processors for adapting said tributary unit pointers.

3. A network element according to claim 1 , wherein said multiplex signals conform to ITU-T recommendations for SDH, wherein said higher order multiplex units comprise virtual containers of a type VC- 4 or VC- 3 and said lower order multiplex units comprise lower order virtual containers of a type VC- 3 , VC- 2 , VC- 12 , or VC- 11 , and wherein said center stage is capable of switching at least virtual containers of the type VC- 3 and said input matrix stage and said output matrix stage are capable of switching at least two of said lower order virtual container types.

4. A network element according to claim 1 , wherein said center stage is a square matrix.

5. A network element according to claim 1 , further comprising a higher order switching matrix connected in series with said lower order switching matrix.

6. A network element according to claim 1 , wherein said input matrix stage and said output matrix stage comprise a number of switch modules, and wherein an input stage module and an associated output stage module are physically arranged on an I/O board of said network element.

7. A network element according to claim 6 , wherein said center stage is physically arranged on at least one matrix board and wherein said I/O board and said matrix board are interconnected through a back panel of said network element.

8. A network element according to claim 6 , wherein said input stage module and said associated output stage module physically arranged on the same I/O board have a direct interconnection for low order connections that remain on the same I/O board.

9. A network element according to claim 1 , wherein said input matrix stage has an expansion of at least 1:2 from its inputs to its outputs.

10. A network element according to claim 1 , which is adapted to perform an optimization of higher order internal connections set up in said center stage by repacking lower order connections set up in said input matrix stage and in said output matrix stage so as to minimize the number of partially filled internal higher order multiplexing units.

11. A network element for a transport network designed for the transport of framed multiplex signals comprising higher order multiplex units capable of carrying lower order multiplex units, wherein the network element comprises a three stage lower order switch matrix comprising:

an input matrix stage and an output matrix stage, wherein the input matrix stage comprises a plurality of hybrid matrices and the output matrix stage comprises a plurality of hybrid matrices, wherein the plurality of hybrid matrices of the input matrix stage and the output matrix stage are designed to switch said lower order multiplex units or higher order multiplex units;

a center stage comprising of a plurality of matrices capable of switching higher order multiplex units only, wherein each of the plurality of center stage matrices is connected to each of the input matrix stage matrices and each of the output matrix stage matrices; and

input/output ports which receive and transmit the framed multiplex signals comprising frames carrying the higher order multiplexing units, wherein each higher order multiplexing unit is capable of carrying lower order multiplexing units.

12. A network element according to claim 11 , wherein said lower order multiplex units are addressed inside said higher order multiplex units by tributary unit pointers and wherein said network element comprises tributary unit pointer processors for adapting said tributary unit pointers.

13. A network element according to claim 11 , wherein said multiplex signals conform to ITU-T recommendations for SDH, wherein said higher order multiplex units comprise virtual containers of a type VC- 4 or VC- 3 and said lower order multiplex units comprise lower order virtual containers of a type VC- 3 , VC- 2 , VC- 12 , or VC- 11 , and wherein said center stage is capable of switching at least virtual containers of the type VC- 3 and said input matrix stage and said output matrix stage are capable of switching at least two of said lower order virtual container types.

14. A network element according to claim 11 , wherein said three stage lower order switch matrix is a Clos matrix.

15. A network element according to claim 11 , further comprising a higher order switching matrix connected in series with said lower order switching matrix.

16. A network element according to claim 11 , wherein said input stage and said output stage comprise a number of switch modules, and wherein an input matrix stage module and an associated output matrix stage module are physically arranged on an I/O board of said network element.

17. A network element according to claim 16 , wherein said plurality of center stage matrices are physically arranged on one or more matrix boards and wherein said I/O board and said one or more matrix boards are interconnected through a back panel of said network element.

18. A network element according to claim 16 , wherein said input stage module and said associated output stage module physically arranged on the same I/O board have a direct interconnection for low order connections that remain on the same I/O board.

19. A network element according to claim 11 , wherein said input matrix stage has an expansion of at least 1:2 from its inputs to its outputs.

20. A network element according to claim 11 , which is adapted to perform an optimization of higher order internal connections set up in said center stage by repacking lower order connections set up in said input matrix stage and in said output matrix stage so as to minimize the number of partially filled internal higher order multiplexing units.

Assignments (6)
SECURITY INTEREST Recorded Jun 1, 2021
From: WSOU INVESTMENTS, LLC
To: OT WSOU TERRIER HOLDINGS, LLC
Reel/Frame 056990/0081 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2020
From: ALCATEL LUCENT
To: WSOU INVESTMENTS, LLC
Reel/Frame 052372/0675 →
RELEASE OF SECURITY INTEREST Recorded Sep 30, 2014
From: CREDIT SUISSE AG
To: ALCATEL LUCENT
Reel/Frame 033868/0001 →
SECURITY AGREEMENT Recorded Jan 30, 2013
From: ALCATEL LUCENT
To: CREDIT SUISSE AG
Reel/Frame 029821/0001 →
CHANGE OF NAME Recorded Jul 18, 2011
From: ALCATEL
To: ALCATEL LUCENT
Reel/Frame 026604/0242 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2005
From: JAKEL, HANS-JORG; BORSCHEL, HARTMUT; BEISEL, WERNER; HUMBLET, PIERRE; SCHOENHERR, BRIAN
To: ALCATEL
Reel/Frame 016798/0666 →