Switching matrix for a telecommunication network element
View Patent ↗Disclosed is a memory-based switching matrix for cross-connecting the content of a plurality of input flows into the content of a plurality of output flows, the input flows being in the form of frames and said content being Time Division Multiplexed or packet data or whatever, the matrix comprising a number of physical memories for memorizing incoming input flows to be output in a predesigned order. The matrix is characterized in that the number of physical memories comprises a first number of memories having a writing role and a second number of memories having a reading role, with the second number being higher than the first number, and in that the role of each memory changes after at least one clock cycle. The arrangement according to the invention saves a number of physical memories with respect to known arrangements.
1. A memory-based switching matrix for cross-connecting a content of a plurality of input flows into a content of a plurality of output flows, said input flows being in the form of frames, said matrix comprising a plurality of physical memories for memorizing incoming input flows to be output in a predesigned order, wherein the plurality of physical memories comprises at least one first physical memory having a writing role and at least one second physical memory having a reading role, wherein a greater number of the physical memories have the reading role than the writing role during a clock cycle, and wherein the role of each of the plurality of physical memories changes after at least one clock cycle.
2. The matrix according to claim 1 , wherein a delay compensator memory is provided for realigning said output flows in the time domain.
3. The matrix according to claim 1 , wherein the plurality of physical memories are single-port reading random access memories.
4. The matrix according to claim 1 , wherein the plurality of physical memories are multi-port reading random access memories.
5. The matrix according to claim 1 , wherein the matrix is implemented by at least one chip.
6. The matrix according to claim 1 , wherein the matrix comprises a dedicated provisioning channel for provisioning cross-connection information.
7. The matrix according to claim 6 , wherein the matrix is implemented by a plurality of chips, each chip being configured in parallel by said provisioning channel.
8. The matrix according to claim 1 , wherein a number of input flows is 64 and a number of output flows is 64.
9. The matrix according to claim 8 , wherein the matrix operates at a writing frequency of 155.5 Mb/s and at a reading frequency of 311 Mb/s.
10. The matrix according to claim 8 , wherein said frames comprise a number of payloads of 384 words, with each word comprising 16 bits.
11. The matrix according to claim 8 , wherein the plurality of physical memories comprises forty physical memories, arranged in eight groups of five physical memories, each group feeding eight output links, and during 384 clock cycles, one physical memory of each group has the writing role and the other four memories have the reading role.
12. A network element comprising at least one memory-based switching matrix according to claim 1 , wherein said network element is a Cross Connect or an Add/drop Multiplexer.
13. A method for cross-connecting a content of a plurality of input flows into a content of a plurality of output flows, the input and output flows being in the form of frames, the method comprising:
memorizing incoming input flows and reading such memorized flows for outputting the memorized flows in a predesigned order,
wherein the memorizing comprises:
memorizing the flows in a plurality of physical memories comprising at least one first physical memory having a writing role and at least one second physical memory having a reading role,
wherein a greater number of the physical memories have the reading role than have the writing role during a clock cycle, and
changing the role of each of the plurality of physical memories after at least one clock cycle.
14. The method according to claim 13 , further comprising delay compensating the cross connected data for realigning the output flows.
15. The method according to claim 13 , wherein the memorizing comprises memorizing data in a plurality of single-port reading random access memories.
16. The method according to claim 13 , wherein the memorizing comprises memorizing data in a plurality of multi-port reading random access memories.
17. The method according to claim 13 , further comprising provisioning the cross connection through a dedicated provisioning channel.
18. The method according to claim 13 , wherein a number of input flows is 64 and a number of output flows is 64.
19. The method according to claim 13 , wherein the writing frequency is 155.5 Mb/s and the reading frequency is 311 Mb/s.
20. The method according to claim 13 , wherein the time division multiplexed frames comprise a number of payloads of 384 words, with each word comprising 16 bits.
21. The method according to claim 13 , wherein the plurality of physical memories comprises forty physical memories, arranged in eight groups of five physical memories, each group feeding eight output links, and during 384 clock cycles, one physical memory of each group has the writing role and the other four physical memories of each group have the reading role.