Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit of the present invention includes, between a power line 1 and a ground line 2 , an NMIS transistor 3 capable of supplying fixed signals with low and high levels to the outside, an NMIS transistor 6 having a source connected to a gate of the NMIS transistor 3 , a PMIS transistor 7 having a drain connected to a gate of the NMIS transistor 6 , and an ESD protection power clamp circuit 14 . If a surge is applied to the power line 1 , the ESD protection power clamp circuit 14 is clamped to pass the surge to the ground line. While the surge is passed, the potential of the power line 1 rises to turn on the three transistors 3, 6 , and 7 . At this time, the NMIS transistor 6 and the PMIS transistor 7 can reduce the gate potential of the NMIS transistor 3 lower than the potential of the power line 1.
1. A semiconductor integrated circuit device comprising:
a power line;
a ground line;
a first PMIS transistor having a source connected to the power line;
a high-level output line connected to a drain of the first PMIS transistor to output a high level signal;
a gate potential control circuit having a NMIS transistor and a second PMIS transistor; and
a power clamp circuit for electrostatic discharge protection connected to the power line and the ground line;
wherein the NMIS transistor has a source connected to the ground line and a gate connected to the high-level output line, and
the second PMIS transistor has a drain connected to the ground line, a source connected to the gate of the first PMIS transistor, and a gate for receiving a signal from a drain of the NMIS transistor.
2. The device of claim 1 ,
wherein the gate potential control circuit further includes at least one third PMIS transistor provided between the drain of the NMIS transistor and the gate of the second PMIS transistor, and
the third PMIS transistor has a drain connected to the ground line, a gate for receiving a signal from the drain of the NMIS transistor, and a source for supplying a signal to the gate of the second PMIS transistor.