Thin film transistor array panel and manufacturing method thereof

1. A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming a data line and a drain electrode on the semiconductor layer;

depositing a passivation layer on the data line and the drain electrode;

forming on the passivation layer a photoresist including a first portion and a second portion;

etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode;

removing the second portion of the photoresist;

depositing a conductive film; and

removing the photoresist to form a pixel electrode,

wherein the second portion of the photoresist is thinner than the first portion of the photoresist.

2. The method of claim 1 , wherein:

the conductive film includes a first portion and a second portion,

the first portion of the conductive film is disposed on the first portion of the photoresist, and

removing the photoresist removes the first portion of the conductive film.

3. The method of claim 2 , wherein the photoresist is formed by using a photo mask comprising a light blocking area, a translucent area, and a light transmitting area.

4. The method of claim 2 , wherein the first portion of the photoresist is reduced in thickness when removing the second portion of the photoresist.

5. The method of claim 4 , wherein removal of the second portion of the photoresist comprises ashing.

6. The method of claim 2 , wherein etching the passivation layer exposes a portion of the data line, and removing the photoresist forms a first contact assistant on the exposed portion of the data line.

7. The method of claim 6 ,

wherein etching the passivation layer comprises etching the gate insulating layer to expose a portion of the gate line, and

wherein removing the photoresist forms a second contact assistant on the exposed portion of the gate line.

8. The method of claim 7 , wherein the first contact assistant and the second contact assistant have edges substantially coinciding with edges of the exposed portion of the data line and edges of the exposed portion of the gate line, respectively.

9. The method of claim 1 , wherein the semiconductor layer, the data line, and the drain electrode are formed by one lithography step.

10. A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming a data line and a drain electrode on the semiconductor layer;

depositing a passivation layer on the data line and the drain electrode;

forming a photoresist on the passivation layer and including a first portion and a second portion;

etching a layer using the photoresist as a mask to expose a portion of the data line or a portion of the gate line;

removing the second portion of the photoresist;

depositing a conductive film; and

removing the photoresist to form a contact assistant on the exposed portion of the data line or on the exposed portion of the gate line,

wherein the second portion of the photoresist is thinner than the first portion of the photoresist.

11. The method of claim 10 , wherein etching the layer comprises etching the passivation layer, and removing the photoresist forms the contact assistant on the exposed portion of the data line.

12. The method of claim 10 , wherein etching the layer comprises etching the passivation layer and the gate insulating layer, and removing the photoresist forms the contact assistant on the exposed portion of the gate line.

13. The method of claim 10 , wherein:

the conductive film includes a first portion and a second portion,

the first portion of the conductive film is disposed on the first portion of the photoresist, and

removing the photoresist removes the first portion of the conductive film.

14. A method for manufacturing a thin film transistor array panel, the method comprising:

forming a gate line on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming a data line and a drain electrode on the semiconductor layer;

depositing a passivation layer on the data line and the drain electrode;

forming a first photoresist;

etching the passivation layer using the first photoresist as a mask to form a first contact hole exposing a portion of the drain electrode and to expose a portion of the gate insulating layer on a portion of the gate line;

transforming the first photoresist into a second photoresist;

etching the passivation layer and the gate insulating layer using the second photoresist as a mask to form a second contact hole and a third contact hole exposing a portion of the gate line and a portion of the data line, respectively;

depositing a conductive film; and

removing the second photoresist to form a pixel electrode.

15. The method of claim 14 , wherein:

the conductive film includes a first portion and a second portion,

the first portion of the conductive film is disposed on the second photoresist, and

removing the second photoresist removes the first portion of the conductive film.

16. The method of claim 15 , wherein the first photoresist is formed by using a photo mask comprising a light blocking area, a translucent area, and a light transmitting areas.

17. The method of claim 15 , wherein removal of the second photoresist comprises ashing.

18. The method of claim 15 , wherein removing the second photoresist forms a contact assistant on the exposed portions of the gate line and the data line.

19. The method of claim 15 , wherein the semiconductor layer, the data line, and the drain electrode are formed by one lithography step.

20. A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming a data line and a drain electrode on the semiconductor layer;

depositing a passivation layer on the data line and the drain electrode;

forming on the passivation layer a photoresist including a first portion and a second portion;

etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode;

removing the second portion of the photoresist;

depositing a conductive film to form a pixel electrode; and

removing the first portion of the photoresist,

wherein the second portion of the photoresist is thinner than the first portion of the photoresist.