Bulk transfer of information on network device
View Patent ↗A network device for processing packets. The network device includes a CPU processing module for transmitting information between at least one memory location on the network device and an external CPU memory location. The CPU processing module includes a first engine for performing bulk transfer of information from the at least one memory location on the network device to the external CPU memory location, wherein all entries of the at least one memory location on the network device are transferred to the external CPU memory location, and a second engine for performing bulk transfer of information from the external CPU memory location to at least one memory location on the switching chip, wherein a plurality of entries from the external CPU memory location is transferred to the memory locations on the switching chip. The second engine uses a bit received from a CPU to determine how entries will be added in the at least one memory location on the switching chip.
1. A network device for processing packets, the network device comprising:
a CPU processing module for transmitting information between at least one memory location on the network device and an external CPU memory location, wherein the CPU processing module comprises:
a first engine for performing bulk transfer of information from the at least one memory location on the network device to the external CPU memory location, wherein all entries of the at least one memory location on the network device are transferred to the external CPU memory location, and
a second engine for performing bulk transfer of information from the external CPU memory location to at least one memory location on network device, wherein a plurality of entries from the external CPU memory location is transferred to the memory locations on the network device and the second engine uses a bit received from a CPU in communication with the CPU processing module to determine whether entries will be added in a forward direction or a backwards direction in the at least one memory location on the network device,
wherein the CPU processing module is configured to receive the bit that is set to one of a forward insertion when a value is being deleted from the at least one memory location on the network device or a backward insertion when a value is being added to the at least one memory location on the network device.
2. The network device of claim 1 , wherein each of the at least one memory location on the network device comprises one of a Random Access Memory location or a Content Addressable Memory location.
3. The network device of claim 1 , wherein a random access memory in each of the at least one memory location on the network device includes entries for storing data.
4. The network device of claim 1 , wherein a content addressable memory in each of the at least one memory location on the network device includes entries for storing data and a corresponding key.
5. The network device of claim 1 , wherein the second engine is configured to receive the bit from the CPU, a starting location of a table data structure in the external CPU memory location, a number of bus cycles per entry, a number of entries to be updated and the starting address of a table in the network device.
6. The network device of claim 5 , wherein the number of bus cycles per entry is rounded up to the next 32-bit boundary and the CPU processing module is configured to receive a rounded-bus cycle from the CPU.
7. The network device of claim 1 , wherein when the bit is set for backward insertion, a starting address of the at least one memory location on the network device is the last entry of the memory location on the network device rather than the first entry of the memory location on the network device.
8. The network device of claim 1 , wherein the at least one memory location on the network device is configured to accept entries from the external CPU memory location that are aligned to a 32-bit boundary.
9. A method for processing packets in a network device, the method comprising:
performing at least one of a first bulk transfer of information from at least one memory location on the network device to an external CPU memory location, wherein all entries of the at least one memory location on the network device are transferred to the external CPU memory location, and a second bulk transfer of information from the external CPU memory location to at least one memory location on the network device, wherein a plurality of entries from the external CPU memory location is transferred to the memory locations on the network device; and
receiving a bit from a CPU in communication with a CPU processing module during the second bulk transfer to determine whether entries will be entered in a forward direction or a backwards direction in the at least one memory location on the network device,
wherein the CPU processing module is configured to receive the bit that is set to one of a forward insertion when a value is being deleted from the at least one memory location on the network device or a backward insertion when a value is being added to the at least one memory location on the network device.
10. The method of claim 9 , further comprising using one of a Random Access Memory or a Content Addressable Memory for the at least one memory location.
11. The method of claim 9 , further comprising receiving a starting location of a table data structure in the external CPU memory location, a number of bus cycles per entry, a number of entries to be updated and the starting address of a table in the network device.
12. The method of claim 11 , further comprising rounding the number of bus cycles per entry up to the next 32-bit boundary, wherein the network device receives a rounded bus cycle from the CPU.
13. The method of claim 9 , wherein when the bit is set for backward insertion, further comprising using a last entry of the memory location on the network device rather than a first entry of the memory location on the network device as the starting address of the at least one memory location on the network device.
14. The method of claim 9 , further comprising accepting by the at least one memory location on the network device entries from the external CPU memory location that are aligned to a 32-bit boundary.
15. An apparatus for processing packets on a network device, comprising:
means for performing at least one of a first bulk transfer of information from at least one memory location on the network device to an external CPU memory location, wherein all entries of the at least one memory location on the network device are transferred to the external CPU memory location, and a second bulk transfer of information from the external CPU memory location to at least one memory location on the network device, wherein a plurality of entries from the external CPU memory location is transferred to the memory locations on the network device; and
means for receiving a bit from a CPU in communication with a CPU processing module during the second bulk transfer to determine whether entries will be added in a forward direction or a backwards direction in the at least one memory location on the network device,
wherein the CPU processing module is configured to receive the bit that is set to one of a forward insertion when a value is being deleted from the at least one memory location on the network device or a backward insertion when a value is being added to the at least one memory location on the network device.
16. The apparatus of claim 15 wherein each of the at least one memory location on the network device comprises one of a Random Access Memory location or a Content Addressable Memory location.
17. The apparatus of claim 15 wherein when the bit is set for backward insertion, a starting address of the at least one memory location on the network device is the last entry of the memory location on the network device rather than the first entry of the memory location on the network device.
18. The apparatus of claim 15 wherein the at least one memory location on the network device is configured to accept entries from the external CPU memory location that are aligned to a 32-bit boundary.