Eliminate false passing of circuit verification through automatic detecting of over-constraining in formal verification
View Patent ↗Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the circuit portion. Embodiments of the invention recognize that if the environment circuit produces a set of outputs that contain a pattern that is not present in the potential constraint set, then the potential constraint set is overconstrained. A verification tool establishes the properties for the environmental circuit based on the potential constraint set. If the verification tool determines that the outputs produced by the environment circuit conflict with the properties of the environment circuit, then the verification tool concludes that the potential constraint set is overconstrained, because the environment circuit produces a pattern that is not present in the potential constraint set. Advantageously, the laborious and error-prone process of manually determining the proper inputs to apply during formal verification is avoided.
1. A method for determining whether a potential constraint set for a circuit under test (CUT) overconstrains inputs that can be applied to the CUT, the method comprising:
allowing a user to describe a potential constraint set for the CUT, wherein the potential constraint set specifies inputs that the user believes can be applied to the CUT by an environment circuit during operation;
establishing, based upon the potential constraint set, a set of conditions for the environment circuit, wherein the set of conditions sets forth limitations on what outputs are expected to be generated by the environment circuit during operation;
applying a set of environmental inputs to the environment circuit to produce a set of environmental outputs;
determining whether the set of environmental outputs violate the set of conditions; and
in response to a determination that the set of environmental outputs violate the set of conditions, concluding that the potential constraint set overconstrains inputs that can be applied to the CUT.
2. The method of claim 1 , wherein the step of determining whether the set of environmental outputs violate the set of conditions is not performed to verify the environment circuit.
3. The method of claim 1 , wherein the set of conditions and the potential constraint set are expressed in a hardware description language (HDL).
4. The method of claim 1 , wherein the step of establishing the set of conditions for the environment circuit comprises:
updating signal names, within the potential constraint set, to reflect names of output signals from the environment circuit.
5. The method of claim 1 , wherein the environmental inputs represent inputs that are expected to be applied to the environment circuit by another circuit during operation, and wherein the method further comprises determining whether the environmental inputs overconstrain inputs that can be applied to the environment circuit by the other circuit during operation.
6. A machine-readable storage medium carrying one or more sequences of instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of:
allowing a user to describe a potential constraint set for a circuit under test (CUT), wherein the potential constraint set specifies inputs that the user believes can be applied to the CUT by an environment circuit during operation;
establishing, based upon the potential constraint set, a set of conditions for the environment circuit, wherein the set of conditions sets forth limitations on what outputs are expected to be generated by the environment circuit during operation;
applying a set of environmental inputs to the environment circuit to produce a set of environmental outputs;
determining whether the set of environmental outputs violate the set of conditions; and
in response to a determination that the set of environmental outputs violate the set of conditions, concluding that the potential constraint set overconstrains inputs that can be applied to the CUT.
7. The machine-readable storage medium of claim 6 , wherein the step of determining whether the set of environmental outputs violate the set of conditions is not performed to verify the environment circuit.
8. The machine-readable storage medium of claim 6 , wherein the set of conditions and the potential constraint set are expressed in a hardware description language (HDL).
9. The machine-readable storage medium of claim 6 , wherein the step of establishing the set of conditions for the environment circuit:
updating signal names, within the potential constraint set, to reflect names of output signals from the environment circuit.
10. The machine-readable storage medium of claim 6 , wherein the environmental inputs represent inputs that are expected to be applied to the environment circuit by another circuit during operation, and wherein execution of the one or more sequences of instructions by the one or more processors further causes the one or more processors to perform the step of:
determining whether the environmental inputs overconstrain inputs that can be applied to the environment circuit by the other circuit during operation.