Integrated circuit devices having a metal-insulator-metal (MIM) capacitor
In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
1 . An integrated circuit device, comprising:
a substrate;
an interlevel-insulating layer on the substrate having a hole therein that exposes the substrate;
a unitary lower electrode of a capacitor disposed on the substrate that has a contact plug portion thereof that is disposed in the hole;
a dielectric layer on the lower electrode of the capacitor; and
an upper electrode of the capacitor on the dielectric layer.
2 . The integrated circuit device of claim 1 , further comprising:
a barrier layer between the contact plug portion of the lower electrode of the capacitor and both the substrate and sidewalls of the interlevel-insulating layer.
3 . The integrated circuit device of claim 2 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
4 . The integrated circuit device of claim 2 , wherein the barrier layer comprises a material that is selected from the group of materials consisting of TiN, TiSiN, TiAlN, TaN, TaSiN, and TaAlN.
5 . The integrated circuit device of claim 2 , wherein the lower electrode of the capacitor is cylindrical.
6 . The integrated circuit device of claim 5 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
7 . The integrated circuit device of claim 1 , further comprising:
a mold layer on the interlevel-insulating layer that has an opening therein through which the lower electrode of the capacitor is received.
8 . The integrated circuit device of claim 7 , wherein the mold layer comprises silicon oxide.
9 . The integrated circuit device of claim 7 , further comprising:
an etch stop layer on the mold layer that has an opening therein through which the lower electrode of the capacitor is received.
10 . The integrated circuit device of claim 9 , wherein the etch stop layer comprises a material selected from the group of materials consisting of silicon oxide, and tantalum oxide.
11 . The integrated circuit device of claim 1 , wherein the dielectric layer comprises a material selected from the group of materials consisting of Al 2 O 3 , Ta 2 O 5 , TiO, (Ba, Sr)TiO 3 , Pb(Zr, Ti)O 3 , and (Pb, La)(Zr, Ti)O 3 .
12 . The integrated circuit device of claim 1 , wherein the upper and lower electrodes of the capacitor comprise a material selected from the group of materials consisting of Pt, Ru, and Ir.
13 . An integrated circuit device, comprising:
a substrate;
an interlevel-insulating layer on the substrate having a hole therein that exposes the substrate;
a barrier layer on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer;
a contact plug disposed in the hole on the barrier layer;
a lower electrode of a capacitor disposed on the contact plug and that engages the contact plug at a boundary therebetween;
a dielectric layer on the lower electrode of the capacitor; and
an upper electrode of the capacitor on the dielectric layer.
14 . The integrated circuit device of claim 13 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
15 . The integrated circuit device of claim 13 , wherein the barrier layer comprises a material that is selected from the group of materials consisting of TiN, TiSiN, TiAlN, TaN, TaSiN, and TaAlN.
16 . The integrated circuit device of claim 13 , wherein the lower electrode of the capacitor is cylindrical.
17 . The integrated circuit device of claim 16 , wherein the barrier layer has a thickness in a range of about 30 Å to about 300 Å.
18 . The integrated circuit device of claim 13 , further comprising:
a mold layer on the interlevel-insulating layer that has an opening therein through which the lower electrode of the capacitor is received.
19 . The integrated circuit device of claim 18 , wherein the mold layer comprises silicon oxide.
20 . The integrated circuit device of claim 18 , further comprising:
an etch stop layer on the mold layer that has an opening therein through which the lower electrode of the capacitor is received.
21 . The integrated circuit device of claim 20 , wherein the etch stop layer comprises a material selected from the group of materials consisting of silicon oxide, and tantalum oxide.
22 . The integrated circuit device of claim 13 , wherein the dielectric layer comprises a material selected from the group of materials consisting of Al 2 O 3 , Ta 2 O 5 , TiO, (Ba, Sr)TiO 3 , Pb(Zr, Ti)O 3 , and (Pb, La)(Zr, Ti)O 3 .
23 . The integrated circuit device of claim 13 , wherein the upper and lower electrodes of the capacitor and the contact plug comprise a material selected from the group of materials consisting of Pt, Ru, and Ir.
24 - 38 . (canceled)