Photodiode circuit with improved response time
View Patent ↗A circuit has a voltage source, a node, a photodetector electrically coupled between the voltage source and the node, a resistor electrically coupled between the node and ground, and a voltage clamp electrically connected to the node, the voltage clamp configured to maintain a reverse bias of the photodetector above a predetermined level.
1. A circuit comprising:
a voltage source;
a node;
a photodetector electrically coupled between the voltage source and the node;
a resistor electrically coupled between the node and ground; and
a voltage clamp electrically connected to the node, the voltage clamp configured to maintain a reverse bias of the photodetector above a predetermined level.
2. The circuit of claim 1 wherein the photodetector is a PIN diode.
3. The circuit of claim 1 wherein the voltage source is Vcc.
4. The circuit of claim 1 wherein the voltage clamp comprises a plurality of bipolar transistors.
5. The circuit of claim 1 wherein the voltage clamp includes at least two bipolar transistors coupled in cascade between the node and ground.
6. The circuit of claim 1 wherein the voltage clamp includes a Zener diode electrically coupled between the node and ground.
7. The circuit of claim 6 further comprising a diode electrically coupled between the Zener diode and ground.
8. The circuit of claim 1 wherein the voltage clamp includes a bandgap voltage reference.
9. The circuit of claim 8 further including a bipolar transistor having a base terminal, wherein the bandgap voltage reference is electrically coupled to the base terminal.
10. The circuit of claim 1 wherein the voltage clamp activates at a first voltage and clamps at a second voltage.
11. A circuit comprising:
a node;
a photodetector coupled to the node in a configuration that is operable to provide a reverse-bias voltage across the photodetector; and
a voltage clamp circuit coupled to the node, the voltage clamp circuit configured to place the node at a clamp voltage that is selected to enable a fast response of the photodetector.
12. The circuit of claim 11 , wherein the photodetector is one of a photodiode, a phototransistor, and a PIN diode.
13. The circuit of claim 11 , wherein the voltage clamp circuit comprises a transistor that is operable to have a base-emitter voltage V BE whereby the clamp voltage is set at approximately V BE above ground potential.
14. The circuit of claim 11 , wherein the voltage clamp circuit comprises a pair of transistors that is operable to have a base-emitter voltage V BE in each of the pair of transistors, and whereby the clamp voltage is set at approximately twice V BE above ground potential.
15. The circuit of claim 11 , wherein the voltage clamp circuit comprises a zener diode operable to produce a zener voltage V Z whereby the clamp voltage is set at approximately V Z above ground potential.
16. The circuit of claim 11 , further comprising:
a resistor coupled to the node in a configuration that is operable to develop a node voltage at the node, the node voltage being determined by the magnitude of a current flowing through the resistor; and wherein
the voltage clamp circuit comprises:
a bandgap voltage reference circuit configured to generate a first voltage reference V 1 ;
a voltage supply configured to provide a voltage V t1 ;
a switch operable to selectively couple the voltage V t1 to the node; and
a logic circuit configured to detect the voltage difference between the first voltage reference V 1 and the node voltage and accordingly place the switch in one of an open and a closed position.
17. A circuit comprising:
a node;
a photodetector coupled to the node in a configuration that is operable to provide a reverse-bias voltage across the photodetector; and
a voltage clamp circuit coupled to the node, the voltage clamp circuit configured to place the node at a clamp voltage that is selected to maintain the reverse-bias voltage across the photodetector at a level wherein the photodetector is operating in a non-fully depleted photoconductive mode.
18. The circuit of claim 17 , wherein the photodetector is a PIN diode and wherein operating in the non-fully depleted photoconductive mode comprises maintaining a capacitance C PIN of the PIN diode below a predetermined level.
19. The circuit of claim 17 , wherein the photodetector is a PIN diode and wherein operating in the non-fully depleted photoconductive mode comprises maintaining a depletion region of the PIN diode above a predetermined level.