IP Library Granted Patent US 7,755,183
Granted Patent B2
US 7,755,183 · App. 11/084,805 · Granted Jul 13, 2010

Wiring board, method of manufacturing the same, and semiconductor device

Assignee: Casio Micronics Co., Ltd.
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Quick Facts
Patent No.
US 7,755,183
App. No.
11/084,805
Granted
Jul 13, 2010
Kind
B2
Abstract

According to this invention, a wiring board includes a conductive pattern formed from leads each of which is formed on an organic layer and has a thickness t larger than a width W.

Claims (27)

1. A wiring board for supporting a semiconductor chip, the wiring board comprising:

a substrate having mutually perpendicular length, width, and thickness directions; and

a conductive pattern formed on the substrate, wherein the conductive pattern includes first wiring pattern portions with a first length along the length direction and elongated rectangular shaped second wiring pattern portions with a second length along the length direction, the second wiring pattern portions having one end portion connected to the first wiring pattern portion and the second wiring pattern portions extending in the length direction to a peripheral portion of the substrate,

the first wiring pattern portions are formed on an area of the substrate in a plane defined by the length and width directions in which the semiconductor chip is mounted on the substrate,

the second wiring pattern portions comprising first parts with said one end portion formed on the first wiring pattern portions such that individual bump electrodes are above respective individual first parts in the thickness direction, and second parts that are formed over the substrate to extend along the length direction beyond the first wiring pattern portions,

the width of the second wiring pattern portions is larger than the thickness of the second wiring pattern portions, and

the width of the first wiring pattern portions is not larger than the thickness of the first wiring pattern portions.

2. The wiring board according to claim 1 , wherein the substrate is formed of polyimide.

3. The wiring board according to claim 1 , wherein the individual bump electrodes are provided on the semiconductor chip and are formed on the first parts of the second wiring pattern portions.

4. The wiring board according to claim 1 , wherein the first wiring pattern portions and the second wiring pattern portions are formed of the same conductive material.

5. The wiring board according to claim 4 , wherein the first wiring pattern portions and the second wiring pattern portions are formed of the same conductive material having a different crystal size.

6. The wiring board according to claim 5 , wherein the first wiring pattern portions are formed of a first conductive material having a crystal size that is smaller than a crystal size of a second conductive material forming the second wiring pattern portions.

7. The wiring board according to claim 4 , wherein the first wiring pattern portions and the second wiring pattern portions are formed of the same conductive material having a different hardness.

8. The wiring board according to claim 7 , wherein the first wiring pattern portions are formed of a first conductive material having a hardness that is harder than a hardness of a second conductive material forming the second wiring pattern portions.

9. The wiring board according to claim 4 , wherein the first wiring pattern portions and the second wiring pattern portions are formed of the same conductive material having a different crystal orientation.

10. The wiring board according to claim 1 , wherein the first wiring pattern portions are formed of a copper and the second wiring pattern portions are formed of copper-alloy, nickel, or chrome.

11. The wiring board according to claim 1 , wherein the second wiring pattern portions have a cross section of a square viewed from the inner area.

12. The wiring board according to claim 1 , wherein the second wiring pattern portions have a cross section of a trapezoidal viewed from the inner area, an upper side of the trapezoidal being short and a lower side of the trapezoidal being long.

13. A semiconductor device comprising:

a substrate having mutually perpendicular length, width, and thickness directions;

a wiring board formed on the substrate; and

a semiconductor chip mounted on the wiring board, wherein the wiring board includes a conductive pattern formed on the substrate,

wherein the conductive pattern includes first wiring pattern portions with a first length along the length direction and elongated rectangular shaped second wiring pattern portions with a second length along the length direction, the second wiring pattern portions having one end portion connected to the first wiring pattern portion and the second wiring pattern portions extending in the length direction to a peripheral portion of the substrate,

the first wiring pattern portions are formed on an area of the substrate in a plane defined by the length and width directions in which the semiconductor chip is mounted on the substrate,

the second wiring pattern portions comprising first parts with said one end portion formed on the first wiring pattern portions such that individual bump electrodes are above respective individual first parts in the thickness direction, and second parts that are formed over the substrate to extend along the length direction beyond the first wiring pattern portions,

the width of the second wiring pattern portions is larger than the thickness of the second wiring pattern portions, and

the width of the first wiring pattern portions is not larger than the thickness of the first wiring pattern portions.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE STREET ADDRESS FROM 10-6 IMAI 3-CHOME TO 10-6, IMAI 3-CHOME PREVIOUSLY RECORDED ON REEL 027357 FRAME 0151. ASSIGNOR(S) HEREBY CONFIRMS THE CORPORATE SEPARATION. Recorded Feb 1, 2012
From: CASCIO MICRONICS CO., LTD.
To: TERAMIKROS, INC.
Reel/Frame 027629/0744 →
CORPORATE SEPARATION Recorded Dec 9, 2011
From: CASCIO MICRONICS CO., LTD.
To: TERAMIKROS, INC.
Reel/Frame 027357/0151 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2005
From: YAMAMOTO, MITSUHIKO
To: CASIO MICRONICS CO., LTD.
Reel/Frame 016402/0513 →
Priority Claims (1)
JP 2004-266923 · Sep 14, 2004 · national
Continuity (1)
Related Publication 20060055021A1 · Mar 16, 2006