Thin film transistor, thin film transistor substrate, and methods for manufacturing the same
View Patent ↗A thin film transistor includes a channel layer of a specific shape, a thermal gradient inducer body, a gate insulating film, a gate electrode and an interlayer insulating film, a source electrode and a drain electrode. The channel layer is formed on a substrate. The channel layer has a nucleation region and a crystal end. The thermal gradient inducer body partially circumscribes the channel layer. The gate insulating film is formed on the substrate, and the channel layer is at least partially covered with the gate insulating film. The gate electrode is formed on the gate insulating film. The interlayer insulating film is formed on the gate insulating film, and the gate electrode is at least partially covered with the interlayer insulating film. The source electrode and the drain electrode are formed on the interlayer insulating film, passed through the gate insulating film and the interlayer insulating film, and electrically connected to the channel layer.
1. A thin film transistor disposed on a substrate, comprising:
a channel layer disposed on the substrate and having a first wide portion and at least one nucleation region;
at least one thermal gradient inducer body disposed on the substrate and enclosing the channel layer;
a gate insulating film disposed on the substrate and covering the channel layer;
a gate electrode disposed on the gate insulating film;
a interlayer insulating film disposed on the gate insulating film and covering the gate electrode; and
a source electrode and a drain electrode disposed on the interlayer insulating film, passed through the gate insulating film and the interlayer insulating film, and electrically connected to the channel layer.
2. The thin film transistor as claimed in claim 1 , wherein the channel layer and the thermal gradient inducer body define a gap.
3. The thin film transistor as claimed in claim 1 , wherein the channel layer is selected from the group consisting of poly-silicon and single silicon.
4. The thin film transistor as claimed in claim 1 , wherein the channel layer is in the shape of tear.
5. The thin film transistor as claimed in claim 1 , wherein the channel layer is of a triangular shape.
6. The thin film transistor as claimed in claim 1 , wherein the channel layer is in the shape of fan.
7. The thin film transistor as claimed in claim 1 , wherein the channel layer is in the shape of trapezoid.
8. The thin film transistor as claimed in claim 1 , wherein the channel layer is in the shape of crown.
9. The thin film transistor as claimed in claim 1 , wherein the thermal gradient inducer body has a wide portion and a narrow portion, and wherein the wide portion is proximal to the crystal end and the narrow portion is proximal to the nucleation region.
10. The thin film transistor as claimed in claim 9 , wherein the thermal gradient inducer body and the channel layer define a variable thickness gap, the thickness of the gap being less at the wide portion than the narrow portion.
11. The thin film transistor as claimed in claim 1 , wherein the channel layer comprises a source region electrically connected to the source electrode, an intermediate region and a drain region electrically connected to the drain electrode.
12. The thin film transistor as claimed in claim 1 , wherein the narrow portion of the thermal gradient inducer body has sawtooth-shaped edges.
13. The thin film transistor as claimed in claim 1 , wherein the nucleation region defines a first transverse width of the channel layer, and the crystal end defines a second transverse width of the channel layer, and the first transverse width is less than the second transverse width.
14. The thin film transistor as claimed in claim 1 , further including:
a source electrode and a drain electrode disposed on the first interlayer insulating film, passed through the gate insulating film and the first interlayer insulating film, and electrically connected to the channel layer; a second interlayer insulating film disposed on the first interlayer insulating film and covering the source electrode and the drain electrode, wherein the second interlayer insulating film defines a contact hole; and
a pixel electrode formed on the second interlayer insulating film and deposited in the contact hole.
15. A method for manufacturing a thin film transistor, comprising the following steps of:
disposing an initial channel layer on the substrate;
patterning the initial channel layer to form a specific shape channel layer and at least one thermal gradient inducer body, wherein the channel layer has a crystal end and a nucleation region, and the thermal gradient inducer body partially circumscribes the specific shape channel layer and has a wide portion and a narrow portion that generally correspond to the crystal end and the nucleation region of the specific shape channel layer;
annealing the specific shape channel layer and the thermal gradient inducer body;
disposing a gate insulating film on the substrate, wherein the specific shape channel layer and the thermal gradient inducer body are generally covered with the gate insulating film;
disposing a gate electrode on the gate insulating film;
implanting one of ion P − and ion N + into the specific shape channel layer to form a source region, an intermediate region and a drain region;
disposing an interlayer insulating film on the gate insulating film, wherein the gate electrode is generally covered with the interlayer insulating film;
forming two contact holes passed through the gate insulating film and the interlayer insulating film to expose the source region and the drain region; and
disposing a source electrode and a drain electrode on the interlayer insulating film, wherein the two contact holes at least partially filled with the source electrode and the drain electrode.
16. The method as claimed in claim 15 , wherein the initial channel layer is deposited on the substrate by using a plasma chemical vapor deposition process.
17. The method as claimed in claim 15 , wherein the specific shape channel layer and the thermal gradient inducer body are formed by using photolithography and etching processes.
18. The method as claimed in claim 15 , wherein the specific shape channel layer is selected from the group consisting of poly-silicon and single silicon.
19. The method as claimed in claim 15 , wherein the narrow portion of the specific shape channel layer has a tip, and crystal grain growth starts in the nucleation region and spreads therefrom towards the crystal end.
20. The method as claimed in claim 15 , wherein the nucleation region defines a first transverse width of the channel layer, and the crystal end defines a second transverse width of the channel layer, and the first transverse width is less than the second transverse width.
21. The method of claim 15 , further including the steps of:
disposing a second interlayer insulating film on the first interlayer insulating film, wherein the source electrode and the drain electrode are generally covered with the second interlayer insulating film;
forming a contact hole in the second interlayer insulating film; and
disposing a pixel electrode on the second interlayer insulating film and deposited in the contact hole.
22. A thin film transistor comprising:
a substrate;
a channel layer disposed on the substrate, the channel layer defining a nucleation region and a crystal end, wherein the nucleation region defines a first transverse width and the crystal end defines a second transverse width, wherein the first transverse width is less than the second transverse width; and
a thermal gradient inducer body disposed on the substrate, wherein the thermal gradient inducer body substantially circumscribes the channel layer, wherein the thermal gradient inducer body and the channel layer define a gap.
23. The thin film transistor of claim 22 , wherein the gap between the channel layer and the thermal gradient inducer body has a first length proximal to the crystal end and a second length proximal to the nucleation region, the first length being less than the second length.
24. The thin film transistor of claim 22 , wherein the thermal gradient inducer body defines a narrow portion and a wide portion, the narrow portion being proximal to the nucleation region and the wide portion being proximal to the nucleation region.
25. The thin film transistor of claim 22 , wherein the nucleation region defines a tip, wherein narrow portion defines an opening that is generally aligned with the tip.