Semiconductor memory device
View Patent ↗A cell array in the semiconductor memory device is divided into two blocks. Each of control signal lines for transmission of control signals are also divided into a first portion and a second portion correspondingly to the blocks. A repeater circuit that relays a control signal is provided between the two portions. The repeater circuit does not output the control signal from the first portion to the second portion, as long as a block that receives the control signal via the first portion is selected.
1. A semiconductor memory device comprising:
a cell array that is divided into n blocks, where n is an integer greater than 1;
a control circuit that outputs a signal to be transmitted to any one of the blocks;
n signal lines including a first signal line that transmits the signal to a first block of the blocks, a second signal line that transmits the signal to a second block of the blocks, and n−2 signal lines that transmit the signal to a corresponding block of the blocks; and
n−1 repeater circuits, wherein an m-th repeater circuit, where m=1, 2, . . . , n−1, is provided between each of m-th signal line and m+1-th signal line, wherein an m-th repeater circuit includes a gate circuit that blocks the signal when the m-th block is selected.
2. The semiconductor memory device according to claim 1 , wherein the gate circuit outputs the signal to an m+1-th signal line when a k-th block, where k=m+1, m+2, . . . , n, is selected.
3. The semiconductor memory device according to claim 1 , wherein the gate circuit blocks the signal based on a block selection signal for selecting any one of the blocks.
4. The semiconductor memory device according to claim 1 , wherein each block is not operated when not selected.
5. A semiconductor memory device comprising:
a cell array that is divided into n blocks, where n is an integer greater than 1;
a control circuit that outputs a signal to be transmitted to any one of the blocks;
n signal lines including a first signal line that transmits the signal to a first block of the blocks, a second signal line that transmits the signal to a second block of the blocks, and n−2 signal lines that transmit the signal to a corresponding block of the blocks; and
n−1 repeater circuits, wherein an m-th repeater circuit, where m=1, 2, . . . , n−1, is provided between each of m-th signal line and m+1-th signal line, wherein the m-th repeater circuit includes a gate circuit that blocks the signal when a k-th block, where k=m+1, m+2, . . . , n, is not selected.
6. The semiconductor memory device according to claim 5 , wherein the gate circuit outputs the signal to the m+1-th signal line when a k-th block, where k=m+1, m+2, . . . , n, is selected.
7. The semiconductor memory device according to claim 5 , wherein the gate circuit blocks the signal based on a block selection signal for selecting any one of the blocks.
8. The semiconductor memory device according to claim 5 , wherein each block is not operated when not selected.
9. A semiconductor memory device comprising:
a cell array that is divided into n blocks, where n is an integer greater than 1;
a control circuit that outputs a signal to be transmitted to any one of the blocks;
m signal lines, where m=2, 3, . . . , n, each of which transmits the signal to at least one block of the blocks; and
a repeater circuit that is provided between a k-th signal line and a k+1-th signal line, where k=1, 2, . . . , m−1, wherein
the repeater circuit includes a gate circuit that blocks the signal when a block to which the signal is transmitted by the k-th signal line is selected.
10. The semiconductor memory device according to claim 9 , wherein the gate circuit outputs the signal to the k+1-th signal line when a block to which the signal is transmitted by the k+1-th signal line is selected.
11. The semiconductor memory device according claim 9 , further comprising another repeater circuit that does not include the gate circuit and outputs the signal irrespective of which block is selected.
12. The semiconductor memory device according to claim 9 , wherein the gate circuit blocks the signal based on a block selection signal for selecting any one of the blocks.
13. The semiconductor memory device according to claim 9 , wherein each block is not operated when not selected.