P channel Rad Hard MOSFET with enhancement implant
View Patent ↗A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base stripes are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. A P type enhancement region is implanted through spaced narrow windows early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) P channel device with very low gate capacitance and very low on resistance.
1. The process of forming a Rad Hard MOSFET comprising the steps of implanting and diffusing a plurality of parallel spaced enhancement strips into the surface of a silicon wafer of one of the conductivity types; and thereafter implanting and diffusing a plurality of channel diffusions of the opposite conductivity type between and partially overlapping the side edges of adjacent ones of said enhancement strips; and thereafter forming source strips of said one conductivity type within each of said channel strips to define invertible channel regions on the opposite sides of each of said channel diffusions; and thereafter forming gate oxide and polysilicon gate strips atop each of said invertible channel regions and each said enhancement strip; and thereafter forming a conductive source contact atop and in contact with each of said source and channel diffusions, wherein said one conductivity type is the P type and said other conductivity type is N type whereby said MOSFET is a P channel device.
2. The process of claim 1 , wherein said channel diffusions are spaced by about 0.6 microns.
3. The process of claim 2 , wherein said polysilicon strips have a width of about 3.2 microns.
4. The process of claim 1 , wherein said enhancement implant has a depth of about 1.5μ.
5. The process of claim 4 , wherein said channel diffusion has a depth about equal to that of said enhancement implant.