Method and system for communicating with memory devices utilizing selected timing parameters from a timing table
View Patent ↗A computational system is disclosed. The computational system includes a controller having a table including a plurality of sets of timing parameters. The plurality of sets of timing parameters are ordered based on a speed rate. The computational system also includes a device accessible to the controller. The controller communicates with the device in accordance with one set of timing parameters selected from the plurality of sets of timing parameters.
1. A method comprising:
selecting, at a memory controller, a first set of timing parameters relating to memory control signals from a plurality of sets of timing parameters associated with a particular memory operation in one or more tables at the memory controller;
communicating with a flash memory device of the computational system by generating memory control signals at the memory controller based on a clock signal and the first set of timing parameters;
determining, at the memory controller, an error rate associated with communicating with the flash memory device;
selecting, at the memory controller, a second set of timing parameters relating to memory control signals from the plurality of sets of timing parameters based on the determined error rate, wherein selecting the second set of timing parameters includes selecting a set of timing parameters faster than the first set of timing parameters when the determined error rate is below a threshold, and selecting a set of timing parameters slower than the first set of timing parameters when the determined error rate is above the threshold; and
communicating with the flash memory device of the computational system by generating memory control signals based on the clock signal and the second set of timing parameters.
2. The method of claim 1 , wherein the plurality of sets of timing parameters are stored in an ordered configuration in accordance with a speed associated with each set of the plurality of sets of timing parameters.
3. The method of claim 1 , wherein the plurality of sets of timing parameters are stored in an ordered configuration from a slowest speed to a fastest speed.
4. The method of claim 1 , wherein at least one of the one or more tables is a soft table.
5. The method of claim 1 , wherein at least one of the one or more tables is a hardware-based table.
6. The method of claim 1 , wherein each set of timing parameters of the plurality of sets of timing parameters comprise values in units of time.
7. The method of claim 1 , wherein the plurality of sets of timing parameters include timing parameters having a read enable pulse width (tRP) and a read enable high hold time (tREH).
8. The method of claim 7 , wherein communicating with the flash memory device includes sending a read enable signal in a low state for a period tRP, followed by a high state for at least a period tREH.
9. A method performed at a memory controller of a computational system, the method comprising:
for each device of a plurality of memory devices of the computational system accessible to the memory controller:
selecting, at the memory controller, a first set of timing parameters relating to memory control signals from a plurality of sets of timing parameters associated with a particular memory operation in one or more tables at the memory controller;
communicating with a first flash memory device of the plurality of memory devices by generating memory control signals at the memory controller based on a clock signal and the first set of timing parameters;
determining, at the memory controller, an error rate associated with communicating with the first flash memory device;
selecting, at the memory controller, a second set of timing parameters relating to memory control signals from the plurality of sets of timing parameters based on the determined error rate, wherein selecting the second set of timing parameters includes selecting a set of timing parameters faster than the first set of timing parameters when the determined error rate is below a threshold, and selecting a set of timing parameters slower than the first set of timing parameters when the determined error rate is above the threshold; and
communicating with the first flash memory device by generating memory control signals based on the clock signal and the second set of timing parameters.
10. A computational system comprising:
a flash memory device; and
a memory controller including a plurality of sets of timing parameters, wherein the memory controller is operable to:
select a first set of timing parameters relating to memory control signals from the plurality of sets of timing parameters associated with a particular memory operation in one or more tables at the memory controller;
communicate with the flash memory device by generating memory control signals based on a clock signal and the first set of timing parameters;
determine an error rate associated with communicating with the flash memory device;
select a second set of timing parameters relating to memory control signals from the plurality of sets of timing parameters based on the determined error rate, wherein selecting the second set of timing parameters includes selecting a set of timing parameters faster than the first set of timing parameters when the determined error rate is below a threshold, and selecting a set of timing parameters slower than the first set of timing parameters when the determined error rate is above the threshold; and
communicate with the flash memory device by generating memory control signals based on the clock signal and the second set of timing parameters.
11. The method of claim 1 , further comprising incrementing to a faster set of timing parameters when the determined error rate remains below the threshold over a period of time.
12. The method of claim 9 , wherein each set of timing parameters of the plurality of sets of timing parameters includes hold times that are stored in an order of shortest hold time to longest hold time.
13. A computational system comprising:
a flash memory device; and
a memory controller including a plurality of sets of timing parameters, wherein the memory controller is operable to:
select a first set of timing parameters relating to memory control signals from the plurality of sets of timing parameters associated with a particular memory operation in one or more tables at the memory controller;
communicate with the flash memory device by generating memory control signals based on a clock signal and the first set of timing parameters;
determine an error rate associated with communicating with the flash memory device;
select a second set of timing parameters relating to memory control signals from the plurality of sets of timing parameters based on the determined error rate, wherein selecting the second set of timing parameters includes selecting a set of timing parameters faster than the first set of timing parameters when the determined error rate is below a threshold; and
communicate with the flash memory device by generating memory control signals based on the clock signal and the second set of timing parameters.