Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal
View Patent ↗In a semiconductor device, a main circuit is operated by a first clock signal, and at least one characteristic evaluating circuit is operated by a second clock signal whose frequency is higher than a frequency of the first clock signal. Also, at least one deterioration detecting circuit is connected to the characteristic evaluating circuit and Is adapted to detect deterioration of the characteristic evaluating circuit.
1. A semiconductor device comprising:
a main circuit operated by a first clock signal;
at least one characteristic evaluating circuit operated by a second clock signal whose frequency is higher than a frequency of said first clock signal; and
at least one deterioration detecting circuit connected to said characteristic evaluating circuit and being adapted to detect deterioration of said characteristic evaluating circuit.
2. The semiconductor device as set forth in claim 1 , further comprising a clock input terminal connected to said main circuit and being adapted to receive said first clock signal from the exterior and transmit said first clock signal to said main circuit.
3. The semiconductor device as set forth in claim 2 , further comprising a frequency multiplier connected between said clock input terminal and said characteristic evaluating circuit, said frequency multiplier being adapted to receive said first clock signal from said clock input terminal to generate said second clock signal.
4. The semiconductor device as set forth in claim 1 , wherein said characteristic evaluating circuit comprises:
a first D-type flip-flop;
a plurality of inverters connected between an output of said first D-type flip-flop and an output of said characteristic evaluating circuit, an output of an intermediate one of said inverters being connected to a data input of said first D-type flip-flop, so that an output signal of the intermediate one of said inverters is latched in said first D-type flip-flop clocked by said second clock signal,
said deterioration detecting circuit comprising:
a coincidence circuit adapted to compare an output signal of said first D-type flip-flop with an output signal of said characteristic evaluating circuit; and
a second D-type flip-flop connected to said coincidence circuit and adapted to latch an output signal of said coincidence circuit clocked by said second clock signal.
5. The semiconductor device as set forth in claim 1 , wherein an output of said deterioration detecting circuit is connected to said main circuit, so that said main circuit can recognize a detection of deterioration of said characteristic evaluating circuit.
6. The semiconductor device as set forth in claim 1 , wherein the at least one characteristic evaluating circuit and the main circuit comprise similar transistors.
7. The semiconductor device as set forth in claim 1 , wherein the main circuit processes a deterioration detect signal output from the at least one deterioration detecting circuit.
8. The semiconductor device as set forth in claim 1 , wherein the at least one deterioration detecting circuit outputs a deterioration detect signal to the main circuit.
9. The semiconductor device as set forth in claim 1 , wherein said characteristic evaluating circuit generates first and second signals depending on the deterioration of said characteristic evaluating circuit, and said deterioration detecting circuit receives said first and second signals to generate a deterioration detection signal.
10. The semiconductor device as set forth in claim 9 , wherein said second signal comprises a delayed signal of said first signal.
11. The semiconductor device as set forth in claim 10 , wherein said detection signal depends upon a difference in delay time between said first and second signals.
12. A method for detecting a deterioration in a semiconductor device comprising:
providing a main circuit operated by a first clock signal;
providing a characteristic evaluating circuit operated by a second clock signal, a frequency of which is higher than a frequency of said first clock signal; and
providing a deterioration detecting circuit connected to said characteristic evaluating circuit adapted to detect deterioration of said characteristic evaluating circuit.
13. The method as set forth in claim 12 , wherein the characteristic evaluating circuit and the main circuit comprise similar transistors.
14. The method as set forth in claim 12 , wherein the main circuit receives a deterioration detect signal output from the deterioration detecting circuit.
15. The method as set forth in claim 12 , wherein the at least one deterioration detecting circuit outputs a deterioration detect signal to the main circuit.
16. The method as set forth in claim 12 , further comprising providing a clock input terminal to said main circuit to receive said first clock signal from an exterior clock.
17. The method as set forth in claim 16 , further comprising providing a frequency multiplier connected between said clock input terminal and said characteristic evaluating circuit receiving said first clock signal from said clock input terminal and generating said second clock signal.
18. The method as set forth in claim 12 , further comprising providing said characteristic evaluating circuit with transistors having one of smaller and larger amplification factors than transistors of said main circuit.