IP Library Granted Patent US 8,194,757
Granted Patent B2
US 8,194,757 · App. 11/089,788 · Granted Jun 5, 2012

Method and system for combining results of mosquito noise reduction and block noise reduction

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Quick Facts
Patent No.
US 8,194,757
App. No.
11/089,788
Granted
Jun 5, 2012
Kind
B2
Abstract

In a video system, a method and system for combining results of mosquito noise reduction and block noise reduction are provided. Noise artifacts may be reduced in a video image by generating a first pixel correction value that combines a first and a second noise reduction parameters utilizing a first combination operation. Combining the first pixel correction value and a third noise reduction parameter utilizing a second combination operation may generate a second pixel correction value. New pixel values may be determined for the video image by adding an original pixel value and the pixel correction value. The noise reduction parameters may correspond to results from mosquito and block noise reduction operations. The first and second combination operations may be selected to be a maximum, a minimum, or an addition of the input parameters based on the sign of the input parameters.

Claims (39)

1. A method for image processing, the method comprising:

performing by one or more processors and/or circuits within an image processing device:

combining results from a first video noise reduction operation and results from a second video noise reduction operation based on a first combination operation, wherein said second video noise reduction operation is different from said first video noise reduction operation;

selecting said first combination operation to be a first addition operation, a first maximum value operation, or a first minimum value operation based on a sign of said results from said first video noise reduction operation and a sign of said results from said second video noise reduction operation; and

generating a first pixel correction value based on results of said selected first combination operation.

2. The method according to claim 1 , comprising correcting at least one pixel value utilizing said generated first pixel correction value.

3. The method according to claim 1 , comprising selecting said first minimum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both negative.

4. The method according to claim 1 , comprising selecting said first maximum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both positive.

5. The method according to claim 1 , comprising selecting said first addition operation when said results from said first noise reduction operation and said results from said second noise reduction operation have different signs.

6. The method according to claim 1 , wherein said results from said first noise reduction operation correspond to results from a horizontal block noise reduction operation.

7. The method according to claim 1 , wherein said results from said second noise reduction operation correspond to results from a vertical block noise reduction operation.

8. The method according to claim 1 , comprising:

combining said generated first pixel correction value and results from a third video noise reduction operation based on a second combination operation;

selecting said second combination operation to be a second addition operation, a second maximum value operation, or a second minimum value operation based on a sign of said generated first pixel correction value and a sign of said results from said third video noise reduction operation; and

generating a second pixel correction value based on results of said selected second combination operation.

9. The method according to claim 8 , comprising correcting at least one pixel value utilizing said generated second pixel correction value.

10. The method according to claim 8 , comprising selecting said second minimum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both negative.

11. The method according to claim 8 , comprising selecting said second maximum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both positive.

12. The method according to claim 8 , comprising selecting said second addition operation when said generated first pixel correction value and said results from said third noise reduction operation have different signs.

13. The method according to claim 8 , wherein said results from said third noise reduction operation correspond to results from a mosquito noise reduction operation.

14. A system for image processing, the system comprising:

one or more circuits that are operable to combine results from a first video noise reduction operation and results from a second video noise reduction operation based on a first combination operation, wherein said second video noise reduction operation is different from said first video noise reduction operation;

said one or more circuits are operable to select said first combination operation to be a first addition operation, a first maximum value operation, or a first minimum value operation based on a sign of said results from said first video noise reduction operation and a sign of said results from said second video noise reduction operation; and

said one or more circuits are operable to generate a first pixel correction value based on results of said selected first combination operation.

15. The system according to claim 14 , wherein said one or more circuits are operable to correct at least one pixel value utilizing said generated first pixel correction value.

16. The system according to claim 14 , wherein said one or more circuits are operable to select said first minimum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both negative.

17. The system according to claim 14 , wherein said one or more circuits are operable to select said first maximum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both positive.

18. The system according to claim 14 , wherein said one or more circuits are operable to select said first addition operation when said results from said first noise reduction operation and said results from said second noise reduction operation have different signs.

19. The system according to claim 14 , wherein said results from said first noise reduction operation correspond to results from a horizontal block noise reduction operation.

20. The system according to claim 14 , wherein said results from said second noise reduction operation correspond to results from a vertical block noise reduction operation.

21. The system according to claim 14 , wherein:

said one or more circuits are operable to combine said generated first pixel correction value and results from a third video noise reduction operation based on a second combination operation;

said one or more circuits are operable to select said second combination operation to be a second addition operation, a second maximum value operation, or a second minimum value operation based on a sign of said generated first pixel correction value and a sign of said results from said third video noise reduction operation; and

said one or more circuits are operable to generate a second pixel correction value based on results of said selected second combination operation.

22. The system according to claim 21 , correct at least one pixel value utilizing said generated second pixel correction value.

23. The system according to claim 21 , wherein said one or more circuits are operable to select said second minimum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both negative.

24. The system according to claim 21 , wherein said one or more circuits are operable to select said second maximum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both positive.

25. The system according to claim 21 , wherein said one or more circuits are operable to select said second addition operation when said generated first pixel correction value and said results from said third noise reduction operation have different signs.

26. The system according to claim 21 , wherein said results from said third noise reduction operation correspond to results from a mosquito noise reduction operation.

Assignments (3)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →