Method of forming metal wiring of semiconductor device
View Patent ↗Disclosed herein is a method of forming a metal wiring of a semiconductor device. A method of forming a metal wiring of a semiconductor device comprises the steps of sequentially forming a first anti-diffusion film, a second interlayer insulating film, a third interlayer insulating film and a capping film on a first interlayer insulating film in which a first metal wiring is formed, patterning the capping film, the third interlayer insulating film, the second interlayer insulating film and the first anti-diffusion film so that the first metal wiring is exposed, thus forming a via hole, patterning the capping film and the third interlayer insulating film so that a given surface of the second interlayer insulating film is exposed on the result in which the via hole is formed, thus forming a metal wiring trench, forming a second anti-diffusion film in the via hole and the metal wiring trench, and sequentially forming copper seed layers in the via hole and the metal wiring trench in which the second anti-diffusion film is formed, and then forming a copper layer by means of an electroplating process, thus forming a via and a metal wiring.
1. A method of forming a metal wiring of a semiconductor device, comprising the steps of:
sequentially forming a first anti-diffusion film, a second interlayer insulating film, a third interlayer insulating film and a capping film on a first interlayer insulating film in which a first metal wiring is formed;
patterning the capping film, the third interlayer insulating film, the second interlayer insulating film and the first anti-diffusion film so that the first metal wiring is exposed, thus forming a via hole;
patterning the capping film and the third interlayer insulating film so that a given surface of the second interlayer insulating film is exposed on the result in which the via hole is formed, thus forming a metal wiring trench;
forming a second anti-diffusion film in the via hole and the metal wiring trench by sequentially performing an ionized sputtering process, a high pressure sputtering process and a bias sputtering process; and
sequentially forming copper seed layers in the via hole and the metal wiring trench in which the second anti-diffusion film is formed, and then forming a copper layer by means of an electroplating process, thus forming a via and a metal wiring.
2. The method as claimed in claim 1 , wherein the ionized sputtering process is performed by applying a low pressure of 3 Torr or less, high power of 5 kW or more, and high magnetic field.
3. The method as claimed in claim 1 , wherein the high pressure sputtering process is performed by applying a high pressure of 3 Torr or more, lower power of 5 kW or less, and no magnetic field.
4. The method as claimed in claim 1 , wherein the bias sputtering process is performed under the condition in which a low pressure of 3 Torr or less is applied, RF of about 250 W to 500 W is applied to the substrate, and remote plasma in which argon (Ar) ions are supplied is used.
5. The method as claimed in claim 1 , wherein the ionized sputtering process includes the steps of:
applying high power and strong magnetic field to a target to ionize a metal;
increasing straightness with the magnetic field; and
depositing a second anti-diffusion film on a top of the metal wiring trench and a bottom of the via hole relatively thickly, and on sidewalls of the metal wiring trench and the via hole relatively thinly.
6. The method as claimed in claim 1 , wherein the high pressure sputtering process includes the steps of:
applying low power to a target on which the process will be performed and low magnetic field to a chamber; and
depositing a second anti-diffusion film on a top corner and a sidewall of the metal wiring trench.