Forced bubble insertion scheme
View Patent ↗A network device for processing packets. The network device includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to a destination port. The memory management unit includes a timer for indicating that a free space should be created on a bus slot between the memory management unit and the egress module, wherein the free space is used for transmitting CPU instructions from the memory management unit to the egress module.
1. A network device for processing packets, the network device comprising:
a memory management unit configured to store packets and perform resource checks on each packet the memory management unit including a timer; and
an egress module configured to perform packet modifications and transmit the packet to a destination port, and
wherein the memory management unit is configured to:
detect an expiration of the timer;
create a non-natural free space or empty slot on a bus between the memory management unit and the egress module when the timer expires and after an end of cell of a packet; and
transmit a CPU instruction from the memory management unit to the egress module on the created free space or empty slot on the bus.
2. The network device according to claim 1 , wherein the memory management unit is configured to create the free space between packets when the timer expires and the memory management unit insert a pending CPU instruction in the created free space.
3. The network device according to claim 1 , wherein the memory management unit is configured to reset the timer after the memory management unit inserts a pending CPU instruction in the free space.
4. The network device according to claim 1 , wherein the memory management unit is configured to create a free space only if there is a pending CPU instruction in the memory management unit.
5. The network device according to claim 1 , wherein the memory management unit is configured to reset the timer when the memory management unit uses a non-natural free space or a free space that was not created by the memory management unit.
6. The network device according to claim 1 , wherein the memory management unit is connected to a CPU processing module via a second bus, wherein the memory management module is configured to accept CPU instructions from the CPU processing module on the second bus.
7. The network device according to claim 1 , wherein the second bus comprises a 32-bit bus.
8. The network device according to claim 1 , wherein the bus from the memory management unit to the egress module is configured as a request based time division multiplexing bus.
9. The network device according to claim 1 , wherein the bus from the memory management unit to the egress module is configured to transmit packets from a high speed port once every six cycles and to transmit packets from a gigabyte port once every 72 cycles.
10. A method for processing packets on a network device, the method comprising the steps of:
initializing a timer in a memory management unit;
creating a non-natural free space or empty slot on a bus between the memory management unit and an egress module when the timer expires and after an end of cell of packet; and
transmitting one or more CPU instructions from the memory management unit to the egress module using the created free space.
11. The method according to claim 10 , further comprising creating the free space between packets on the bus when the timer expires and inserting a pending CPU instruction in the created free space.
12. The method according to claim 10 , further comprising resetting the timer after the memory management unit inserts a pending CPU instruction in the free space.
13. The method according to claim 10 , further comprising creating the free space if there is a pending CPU instruction in the memory management unit.
14. The method according to claim 10 , further comprising resetting the timer every time the memory management unit uses a free space that was not created by the memory management unit.
15. The method according to claim 10 , further comprising accepting CPU instructions from the CPU processing module on a second bus.
16. The method according to claim 10 , further comprising configuring the bus from the memory management unit to the egress module as a request-based time division multiplexing bus.
17. The method according to claim 10 , further comprising configuring the bus from the memory management unit to the egress module to transmit packets from a high speed port once every six cycles to transmit packets from a gigabyte port once every 72 cycles.
18. An apparatus for processing packets in a network device, the apparatus comprising a memory management unit, the apparatus configured to:
initialize a timer in a memory management unit;
create a non-natural free space or empty slot on a bus between the memory management unit and an egress module when the timer expires and after an end of cell of packet; and
transmit one or more CPU instructions from the memory management unit to the egress module using the created free space.