Apparatus and method of analog-to-digital conversion
View Patent ↗An analog-to-digital conversion apparatus includes a register group, a selecting section and an A/D conversion section. The register group has a plurality of registers holding a plurality of channel specification data, respectively. The selecting section is connected with a plurality of analog channels, and sequentially selects the plurality of analog channels for analog-to-digital (A/D) conversion continuously without any idling time based on the plurality of channel specification data held by the plurality of registers. The A/D conversion section carries out the A/D conversion of an analog signal on each of the analog channels selected by the selecting section into a digital signal.
1. An analog-to-digital conversion apparatus, comprising:
a register group comprising a plurality of registers holding a plurality of channel specification data, respectively;
a selecting section connected with a plurality of analog channels, and configured to sequentially select said plurality of analog channels for analog-to-digital (A/D) conversion continuously without any idling time based on said plurality of channel specification data held by said plurality of registers; and
an A/D conversion section configured to carry out the A/D conversion of an analog signal on each of said analog channels selected by said selecting section into a digital signal,
wherein said A/D conversion section issues a conversion end trigger signal immediately before end of said A/D conversion to a last analog input channel for each of said plurality of channel specification data, and
wherein said plurality of channel specification data, having been latched by said plurality of registers, are shifted between said plurality of registers in response to said conversion trigger signal.
2. The analog-to-digital conversion apparatus according to claim 1 , wherein each of said plurality of channel specification data specifies a single analog input channel.
3. The analog-to-digital conversion apparatus according to claim 1 , wherein each of said plurality of channel specification data specifies at least one analog input channel, and when said channel specification data specifies at least two analog input channels, the at least two analog input channels are independently specified.
4. The analog-to-digital conversion apparatus according to claim 1 , wherein said plurality of channel specification data having latched by said plurality of registers are circulated between said plurality of registers in response to said conversion trigger signal.
5. The analog-to-digital conversion apparatus according to claim 1 , further comprising:
a buffer in which said A/D conversion section stores a result of said A/D conversion;
a memory; and
a Direct Memory Access unit configured to transfer said A/D conversion result stored in said buffer to said memory.
6. The analog-to-digital conversion apparatus according to claim 1 , further comprising:
a central processing unit configured to set said channel specification data to each of said plurality of registers and to issue a conversion instruction to said A/D conversion section such that said A/D conversion section carries out said A/D conversion.
7. The analog-to-digital conversion apparatus according to claim 1 , further comprising:
a buffer in which said A/D conversion section stores a result of said A/D conversion;
a bus; and
a central processing unit configured to transfer said A/D conversion result stored in said buffer onto said bus.
8. An analog-to-digital conversion apparatus, comprising:
a register group comprising a plurality of registers holding a plurality of channel specification data, respectively;
a selecting section connected with a plurality of analog channels, and configured to sequentially select said plurality of analog channels for analog-to-digital (A/D) conversion continuously without any idling time based on said plurality of channel specification data held by said plurality of registers;
an A/D conversion section configured to carry out the A/D conversion of an analog signal on each of said analog channels selected by said selecting section into a digital signal, wherein said A/D conversion section issues a conversion end trigger signal immediately before end of said A/D conversion to a last analog input channel for each of said plurality of channel specification data;
a memory configured to store said channel specification data; and
a Direct Memory Access unit configured to read out new channel specification data from said memory and to set to a last one of said plurality of registers in response to said conversion trigger signal.
9. The analog-to-digital conversion apparatus according to claim 8 , wherein each of said plurality of channel specification data specifies a single analog input channel.
10. The analog-to-digital conversion apparatus according to claim 8 , wherein each of said plurality of channel specification data specifies at least one analog input channel, and when said channel specification data specifies at least two analog input channels, the at least two analog input channels are independently specified.
11. The analog-to-digital conversion apparatus according to claim 8 , further comprising:
a buffer in which said A/D conversion section stores a result of said A/D conversion;
a memory; and
a Direct Memory Access unit configured to transfer said A/D conversion result stored in said buffer to said memory.
12. The analog-to-digital conversion apparatus according to claim 8 , further comprising:
a central processing unit configured to set said channel specification data to each of said plurality of registers and to issue a conversion instruction to said A/D conversion section such that said A/D conversion section carries out said A/D conversion.
13. The analog-to-digital conversion apparatus according to claim 8 , further comprising:
a buffer in which said A/D conversion section stores a result of said A/D conversion;
a bus; and
a central processing unit configured to transfer said A/D conversion result stored in said buffer onto said bus.
14. An analog-to-digital conversion apparatus, comprising:
a register group comprising a plurality of registers holding a plurality of channel specification data, respectively;
a selecting section connected with a plurality of analog channels, and configured to sequentially select said plurality of analog channels for analog-to-digital (A/D) conversion continuously without any idling time based on said plurality of channel specification data held by said plurality of registers;
an A/D conversion section configured to carry out the A/D conversion of an analog signal on each of said analog channels selected by said selecting section into a digital signal;
a central processing unit configured to set new channel specification data to a last one of said plurality of registers in response to a conversion trigger signal;
a buffer in which said A/D conversion section stores a result of said A/D conversion;
a memory; and
a Direct Memory Access unit configured to transfer said A/D conversion result stored in said buffer to said memory.
15. The analog-to-digital conversion apparatus according to claim 14 , wherein each of said plurality of channel specification data specifies a single analog input channel.
16. The analog-to-digital conversion apparatus according to claim 14 , wherein each of said plurality of channel specification data specifies at least one analog input channel, and when said channel specification data specifies at least two analog input channels, the at least two analog input channels are independently specified.
17. The analog-to-digital conversion apparatus according to claim 14 , further comprising:
a central processing unit configured to set said channel specification data to each of said plurality of registers and to issue a conversion instruction to said A/D conversion section such that said A/D conversion section carries out said A/D conversion.
18. The analog-to-digital conversion apparatus according to claim 14 , further comprising:
a bus; and
a central processing unit configured to transfer said A/D conversion result stored in said buffer onto said bus.
19. An analog-to-digital conversion method, comprising:
making one of a plurality of channel specification data available;
selecting one of a plurality of analog channels for A/D conversion to be carried out based on said available channel specification data;
carrying out said A/D conversion of an analog signal on the selected analog channel into a digital signal; and
making a next one of said plurality of channel specification data available immediately before said A/D conversion for said available channel specification data ends,
wherein each of said plurality of channel specification data specifies two of said analog input channels, and one is an A/D conversion start channel and the other is an A/D conversion end channel, and
said A/D conversion is carried out to said analog signal on each of said analog input channels between said A/D conversion start channel and said A/D conversion end channel, wherein said carrying out said A/D conversion comprises:
issuing a conversion end trigger signal immediately before end of said A/D conversion to a last analog input channel for said available channel specification data, and
said making a next one comprises:
making said next one of said plurality of channel specification data available in response to said conversion end trigger signal.
20. An analog-to-digital conversion apparatus comprising:
a register group having a plurality of registers holding a plurality of channel specification data, respectively;
a selecting section connected with a plurality of analog channels, and configured to sequentially select said plurality of analog channels for analog-to-digital (A/D) conversion continuously without any idling time based on said plurality of channel specification data held by said plurality of registers; and
an A/D conversion section configured to carry out the A/D conversion of an analog signal on each of said analog channels selected by said selecting section into a digital signal, and to issue a conversion end trigger signal immediately before end of said A/D conversion to a last analog input channel for each of said plurality of channel specification data such that said available channel specification data is shifted among said plurality of channel specification data,
wherein each of said plurality of channel specification data specifies two of said analog input channels, and one is an A/D conversion start channel and the other is an A/D conversion end channel, and
said A/D conversion is carried out to said analog signal on each of said analog input channels between said A/D conversion start channel and said A/D conversion end channel.