Low latency digital filter and method
View Patent ↗A digital filter pre-calculates C(1)*S(n−1), C(2)*S(n−2) . . . C(p−1)*S(n−p+1), prior to the arrival of sample S(n). As such y ( n ) = ∑ k = 0 k = p - 1 C ( k ) * S ( n - k ) may be calculated as a result of a single further multiply and accumulate operation, upon arrival of the symbol S(n). This, significantly reduces the latency of the filter.
1. A digital filter, comprising a symbol buffer having p−1 storage locations for storing arriving symbols, a coefficient memory having p−1 storage locations;
a counter for counting from k=0 to p−1;
a multiply and accumulate (MAC) block for multiplying and accumulating C(k)*S(n−k) from said storage locations of said symbol buffer and said coefficient memory;
said counter providing control signals to cause said MAC block to calculate,
∑
k
=
1
k
=
p
-
1
C
(
k
)
*
S
(
n
-
k
)
between the arrival of the (n−1) th and n th symbols; and, upon arrival of the n th of said symbols, calculating
Y
(
n
)
=
∑
k
=
0
k
=
p
-
1
C
(
k
)
*
S
(
n
-
k
)
;
and
wherein each location of said symbol buffer and said coefficient memory each store two real values; and
wherein said counter further provides control signals to cause said MAC block to calculate,
∑
k
=
1
k
=
p
-
1
C
(
k
+
8
)
*
S
(
n
-
8
-
k
)
between the arrival of the n−1 th and n th of said symbols;
between the arrival of the n−1 th and n th of said symbols; and upon arrival of the n th of said symbols, calculates
Y
(
n
)
=
∑
k
=
0
k
=
p
-
1
S
(
n
-
k
-
8
)
*
C
(
k
+
8
)
.
2. The filter of claim 1 , wherein said symbol buffer further comprises an advance input for shifting currently stored symbols within said buffer to adjacent ones of said storage locations of said symbol buffer.
3. The filter of claim 1 , further comprising a selector in communication with said counter and interconnecting said symbol buffer to select one of said p−1 symbol buffer locations for presentation to said MAC block.
4. The filter of claim 1 , wherein said symbol buffer and said coefficient memory stores complex values, and wherein said MAC block calculates complex products of values in said symbol buffer and said coefficient memory.
5. The filter of claim 4 , wherein said MAC block comprises four multipliers and two adders to calculates said complex products of said complex values stored in said coefficient memory and said complex values stored in said symbol buffer.
6. The filter of claim 1 , wherein said MAC block comprises a multiplier to simultaneously calculate the real product of one of said two real coefficients stored in said coefficient memory and one of said two real symbols stored in said symbol buffer, and a further multiplier to calculate the real product of the other of said two real coefficients stored in said coefficient memory and the other of said two real symbols stored in said symbol buffer.
7. The filter of claim 1 , further comprising a symbol clock generator, in communication with said counter to reset said counter upon receipt of one of said symbols.
8. The filter of claim 1 , further comprising a logic block interconnected with said coefficient memory to adaptively vary said coefficients with each of said symbols S(n).
9. A q tap filter, comprising two of said filters of claim 2 , wherein the symbol buffer of said first filter is interconnected to the symbol buffer of the second of said two filters to provide one of its values to the symbol buffer of the second filter, as a buffer advance signal is received at said advance input.
10. A double precision filter, comprising a filter as claimed in claim 6 , and a summer for summing the output of said multiplier and said further multiplier to form a double precision output.
11. A q tap filter, comprising:
two filters, each of said two filters comprising:
a counter for counting from k=0 to p−1;
a multiply and accumulate (MAC) block for multiplying and accumulating C(k)*S(n−k) from said storage locations of said symbol buffer and said coefficient memory;
said counter providing control signals to cause said MAC block to calculate,
∑
k
=
1
k
=
p
-
1
C
(
k
)
*
S
(
n
-
k
)
between the arrival of the (n− 1 ) th and n th symbols and upon arrival of the n th of said symbols, calculating
Y
(
n
)
=
∑
k
=
0
k
=
p
-
1
C
(
k
)
*
S
(
n
-
k
)
,
wherein said symbol buffer further comprises an advance input for shifting currently stored symbols within said buffer to adjacent ones of said storage locations of said symbol buffer; and
wherein the symbol buffer of said first filter is interconnected to the symbol buffer of the second of said two filters to provide one of its values to the symbol buffer of the second filter, as a buffer advance signal is received at said advance input; and
a symbol buffer having p−1 storage locations for storing arriving symbols, a coefficient memory having p−1 storage locations.
12. The filter of claim 11 , further comprising a selector in communication with said counter and interconnecting said symbol buffer to select one of said p−1 symbol buffer locations for presentation to said MAC block.
13. The filter of claim 11 , wherein said symbol buffer and said coefficient memory stores complex values, and wherein said MAC block calculates complex products of values in said symbol buffer and said coefficient memory.
14. The filter of claim 13 , wherein said MAC block comprises four multipliers and two adders to calculates said complex products of said complex values stored in said coefficient memory and said complex values stored in said symbol buffer.
15. The filter of claim 11 , wherein each location of said symbol buffer and said coefficient memory each store two real values.
16. The filter of claim 15 , wherein said MAC block comprises a multiplier to simultaneously calculate the real product of one of said two real coefficients stored in said coefficient memory and one of said two real symbols stored in said symbol buffer, and a further multiplier to calculate the real product of the other of said two real coefficients stored in said coefficient memory and the other of said two real symbols stored in said symbol buffer.
17. The filter of claim 15 , wherein said counter further provides control signals to cause said MAC block to calculate,
∑
k
=
1
K
=
p
-
1
C
(
k
+
8
)
*
S
(
n
-
8
-
k
)
between the arrival of the n−1 th and n th of said symbols;
between the arrival of the n−1 th and n th of said symbols; and, upon arrival of the n th of said symbols, calculates
Y
(
n
)
=
∑
K
=
0
K
=
p
-
1
S
(
n
-
k
-
8
)
*
C
(
k
+
8
)
.
18. The filter of claim 11 , further comprising a symbol clock generator, in communication with said counter to reset said counter upon receipt of one of said symbols.
19. A double precision filter, comprising:
a digital filter, said digital filter comprising:
a symbol buffer having p− 1 storage locations for storing arriving symbols, a coefficient memory having p− 1 storage locations;
a counter for counting from k=0 to p−1;
a multiply and accumulate (MAC) block for multiplying and accumulating C(k)*S(n−k) from said storage locations of said symbol buffer and said coefficient memory;
said counter providing control signals to cause said MAC block to calculate,
∑
k
=
1
k
=
p
-
1
C
(
k
)
*
S
(
n
-
k
)
between the arrival of the (n−1) th and n th symbols and, upon arrival of the n th of said symbols, calculating
Y
(
n
)
=
∑
k
=
0
k
=
p
-
1
C
(
k
)
*
S
(
n
-
k
)
;
wherein each location of said symbol buffer and said coefficient memory each store two real values;
wherein said MAC block comprises a multiplier to simultaneously calculate the real product of one of said two real coefficients stored in said coefficient memory and one of said two real symbols stored in said symbol buffer, and a further multiplier to calculate the real product of the other of said two real coefficients stored in said coefficient memory and the other of said two real symbols stored in said symbol buffer; and
a summer for summing the output of said multiplier and said further multiplier to form a double precision output.